Sony MZ-E80 Service Manual page 17

MAIN BOARD IC601 CXD2663GA
(DIGITAL SIGNAL PROCESSOR, DIGITAL SERVO SIGNAL PROCESSOR, EFM/ACIRC ENCODER/DECODER,
SHOCK PROOF MEMORY CONTROLLER, ATRAC ENCODER/DECODER, D/A CONVERTER, 16M BIT D-RAM)
Pin No. Pin Name
1 VDCO
2 MNT0
3 MNT1
4 MNT2
5 MNT3
6 SWDT
7 SCLK
8 XLAT
9 VSCO
10 SRDT
11 SENS
12 XRST
13 SQSY
14 MTFLGL
15 TST1
16 XINT
17 TST2
18 VDIOSC
19 OSCI
20 OSCO
21 VSIOSC
22 DAVSSL
23 VREFL
24 AOUTL
25 DAVDDL
26 DAVDDR
27 AOUTR
28 VREFR
29 DAVSSR
30 VSC1
31 XTSL
32, 33 TST3, TST4
34 DOUT
35 DT72
36, 37 VDC1, VDC2
38 DATAI
39 to 41 TST5 to TST7
42 DADT
I/O
— Power supply terminal (+2V) (for internal logic)
Signal indicating the speed follow-up spinning mode output to the system controller (IC801)
O
"H": speed follow-up spinning mode
O Sled motor operation monitor signal output to the system controller (IC801) "H": monitor drive
O Speed limiter signal output to the system controller (IC801)
Window signal to detect an inverse trigger edge output to the system controller (IC801)
O
"H": edge detectable
I Writing data input from the system controller (IC801)
I Serial clock signal input from the system controller (IC801)
I Serial data latch pulse input from the system controller (IC801)
— Ground terminal (for internal logic)
O Reading data output to the system controller (IC801)
O Internal status (SENSE) output to the system controller (IC801)
System reset signal input from the MPC1830ADTB (IC901) "L": reset
I
For several hundreds msec. after the power supply rises, "L" is input, then it changes to "H"
Subcode Q sync (SCOR) output the system controller (IC801)
O
"L": is output every 13.3 msec Almost all, "H" is output
Muting applied to analog signal input in non-signal status causes the signal to be "H"
O
automatically Not used
I Input terminal for the test (fixed at "L")
O Interrupt status output to the system controller (IC801)
I Input terminal for the test (fixed at "L")
— Power supply terminal (+2.4V) (for oscillator cell)
I System clock (512Fs=22.5792 MHz) input terminal
O System clock (512Fs=22.5792 MHz) output terminal
— Ground terminal (for oscillator cell)
— Ground terminal (for internal D/A converter L-ch)
O Reference voltage output terminal (for internal D/A converter L-ch)
O Playback analog signal (L) output to the headphone amplifier (IC301)
— Power supply terminal (+2.4V) (for internal D/A converter L-ch)
— Power supply terminal (+2.4V) (for internal D/A converter R-ch)
O Playback analog signal (R) output to the headphone amplifier (IC301)
O Reference voltage output terminal (for internal D/A converter R-ch)
— Ground terminal (for internal D/A converter R-ch)
— Ground terminal (for internal logic)
Input terminal for the system clock frequency setting
I
"L": 45.1584 MHz, "H": 22.5792 MHz (fixed at "H" in this set)
I Input terminal for the test (normally : fixed at "L")
O Digital audio signal output terminal when playback mode Not used (open)
O Not used (open)
— Power supply terminal (+2V) (for internal logic)
I Input terminal of external audio data to the internal D/A converter Not used (open)
I Input terminal for the test (normally : fixed at "L")
O Playback data signal output to the external D/A converter Not used (open)
Description
– 29 –
"L": limiter on