Chipset Overview - Supermicro H8DC8 User Manual

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Chipset Overview

The H8DC8/H8DCi serverboard is based on the nVidia nForce Pro 2200/2050 and
AMD 8132 chipset. The nVidia nForce Pro 2200/2050 functions as Media and Com-
munications Processors (MCPs) and the AMD 8132 as a PCI-X Tunnel. Controllers
for the system memory are integrated directly into the AMD Opteron processors.
2200 Media and Communications Processor
This MCP is a single-chip, high-performance HyperTransport peripheral controller.
The 2200 includes a 20-lane PCI Express interface, an AMD Opteron 16-bit Hyper
Transport interface link, a four-port Serial ATA interface, a dual ATA133 bus master
interface, a USB 2.0 interface and support for 32-bit PCI slots. This hub connects
directly to CPU#1 and the 2050 MCP. The GLAN#1 port connects directly to the
2200 MCP.
2050 Media and Communications Processor
The 2050 is pin-to-pin compatible with the 2200. It includes a PCI Express inter-
face with 20 lanes and an AMD Opteron 16-bit Hyper Transport interface link. The
GLAN#2 connects directly to the 2050 MCP.
8132 HyperTransport PCI-X Tunnel
This hub includes AMD-specifi c technology that provides two PCI-X bridges with
each bridge supporting a 64-bit data bus as well as separate PCI-X operational
modes and independent transfer rates. Each bridge supports up to fi ve PCI masters
that include clock, request and grant signals. This hub connects to the processors
and through them to system memory.
HyperTransport Technology
HyperTransport technology is a high-speed, low latency point to point link that was
designed to increase the communication speed by a factor of up to 48x between
integrated circuits. This is done partly by reducing the number of buses in the
chipset to reduce bottlenecks and by enabling a more effi cient use of memory in
multi-processor systems. The end result is a signifi cant increase in bandwidth
within the chipset.
Chapter 1: Introduction
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