Circuit Description; Receiver Circuits; Antenna Switching Circuit (Main Unit); Squelch Attenuator Circuit (Main Unit) - Icom IC-2200H Service Manual

SECTION 4

4-1 RECEIVER CIRCUITS

4-1-1 ANTENNA SWITCHING CIRCUIT
(MAIN UNIT)
The antenna switching circuit functions as a low-pass filter
while receiving and a resonator circuit while transmitting.
The circuit does not allow transmit signals to enter receiver
circuits.
Received signals enter the antenna connector and pass
through the low-pass filter (L47, L48, C208, C210, C217).
The filtered signals are passed through the λ/4 type anten-
na switching circuit (D16, D19, L45, L46) and limiter circuits
(D15). The signals are then applied to the squelch attenua-
tor circuit.
4-1-2 SQUELCH ATTENUATOR CIRCUIT
(MAIN UNIT)
The attenuator circuit attenuates the signal strength to a
maximum of 10 dB to protect the RF amplifier from distortion
when excessively strong signals are received.
The current flow of the antenna switching circuit (D16, D19)
is controlled by the [SQL] control via the attenuator con-
troller (IC6a, D18). When the [SQL] control is rotated clock-
wise deeper than 12 o'clock, the current of D16 and D19 is
increased. In this case, D16 and D19 act as an attenuator.
4-1-3 RF CIRCUIT (MAIN UNIT)
The RF circuit amplifies signals within the range of frequen-
cy coverage and filters out-of-band signals.
The signals from the squelch attenuator circuit pass through
the tunable bandpass filter (D13). The filtered signals are
amplified at the RF amplifier (Q27) and then enter another
three-stage bandpass filters (D9–D11) to suppress unwant-
ed signals. The filtered signals are applied to the 1st mixer
circuit (Q19).
• 2ND IF AND DEMODULATOR CIRCUIT
"SQLIN" signal from
the D/A converter IC
(IC5, pin 11)
AF signal "DETO" AM/FM
selector

CIRCUIT DESCRIPTION

AM
detector
8
Active
filter
FM
detector
9
IC12
The tunable bandpass filters (D13–D16) employ varactor
diodes to tune the center frequency of the RF passband for
wide bandwidth receiving and good image response rejec-
tion. These diodes are controlled by the CPU (LOGIC unit;
IC1) via the D/A convertor (IC5).
4-1-4 1ST MIXER AND 1ST IF CIRCUITS
(MAIN UNIT)
The 1st mixer circuit converts the received signals to a fixed
frequency of the 1st IF signal with the PLL output frequency.
By changing the PLL frequency, only the desired frequency
will pass through a pair of crystal filters at the next stage of
the 1st mixer.
The RF signals from the bandpass filter are applied to the
1st mixer circuit (Q19). The applied signals are mixed with
the 1st LO signal coming from the RX-VCO circuit (Q7, D5,
D38) to produce a 21.7 MHz 1st IF signal. The 1st IF signal
passes through a pair of crystal filters (FI3, FI4) to suppress
out-of-band signals. The filtered signal is amplified at the 1st
IF amplifier (Q16), and applied to the 2nd IF circuit via the
limiter circuit (D29).
4-1-5 2ND IF AND DEMODULATOR CIRCUITS
(MAIN unit)
The 2nd mixer circuit converts the 1st IF signal to a 2nd IF
signal. A double-conversion superheterodyne system
improves the image rejection ratio and obtains stable receiv-
er gain.
The 1st IF signal from the IF amplifier (Q16) is applied to the
2nd mixer section of the FM IF IC (IC4, pin 16) and is then
mixed with the 2nd LO signal for conversion to a 450 kHz
2nd IF signal.
IC4 contains the 2nd mixer, limiter amplifier, quadrature
detector, S-meter detector, active filter and noise amplifier
circuits, etc. A frequency from the PLL reference oscillator is
used for the 2nd LO signal (21.25 MHz).
Q37, Q38
FI1
FI2
7
Noise
Noise
comp.
detector
Limiter
amp.
RSSI
10 11 12
R5V
X2
4 - 1
2nd IF filter
450 kHz
(for wide)
PLL IC
16
(for narrow)
2
3
Mixer
IC4 TA31136FN
13 16
1st IF from the
IF amplifier (Q16)
"NOIS" signal to the CPU
(FRONT unit; IC1, pin 26)
"SD" signal to the CPU
(FRONT unit; IC1, pin 4)
X1
21.25 MHz
1
IC1