Chipset; Intel 7500 I/O Hub (Ioh); Ioh Quickpath Interconnect (Qpi); Pcie 2.0 - Dell PowerEdge M910 Technical Manual

8 Chipset

The PowerEdge M910 system board incorporates the Intel 7510 chipset for I/O and processor
interfacing. The 7510 chipset is designed to support the Intel Xeon processor E7-8800, E7-4800 and
E7-2800 product families, Intel Xeon processor 6500 and 7500 series, Intel QPI Interconnect, DDR3
memory technology and PCIe 2.0. The 7510 chipset consists of the IOH QuickPath Interconnect
(QPI), Intel 7500 Scalable Memory Buffer and the ICH10 South Bridge.

Intel 7500 I/O Hub (IOH)

The PowerEdge M910 system board incorporates an Intel 7500 series IOH to provide a link
between the 4S processors and the I/O components. The main components of the IOH consist of
two full-width QPI links (one to each processor), 36 lanes of PCIe 2.0 and a x4 DMI link to connect
directly to the ICH10 (Intel I/O Controller Hub 10) South Bridge.

IOH QuickPath Interconnect (QPI)

The QPI architecture consists of serial point‐to‐point interconnects for the processors and the IOH.
The PowerEdge M910 has a total of four QPI links including one link connecting the processors and
links connecting both processors with the IOH. Each link consists of 20 lanes (full‐width) in each
direction with a link speed of 6.4GT/s. An additional lane is reserved for a forwarded clock. Data is
sent over the QPI links as packets.
The QPI architecture features the following four layers:

The Physical layer consists of the actual connection between components. It supports Polarity
Inversion and Lane Reversal for optimizing component placement and routing.

The Link layer is responsible for flow control and the reliable transmission of data.

The Routing layer is responsible for the routing of QPI data packets.

Finally, the Protocol layer is responsible for high‐level protocol communications, including the
implementation of a MESIF (Modify, Exclusive, Shared, Invalid, Forward) cache coherence
protocol.

PCIe 2.0

PCIe is a serial point‐to‐point interconnect for I/O devices. PCIe 2.0 doubles the signaling bit rate of
each lane from 2.5Gbps to 5Gbps. Each of the PCIe ports is backward‐compatible with 1.0 transfer
rates.

Direct Media Interface

The Direct Media Interface (DMI) (previously called the Enterprise Southbridge Interface) connects
the Intel 7500 Legacy IOH with the Intel I/O Controller Hub (ICH). The DMI is equivalent to an x4
PCIe 1.0 link with a transfer rate of 1Gbps in each direction.

Intel I/O Controller Hub 10

The Intel I/O Controller Hub 10 (ICH10) is a highly integrated I/O controller, supporting the
following functions:

Six x1 PCIe 1.0 ports, with the capability of combining ports 1–4 as a x4 link

PCI Bus 32‐bit Interface Rev 2.3 running at 33MT/s

Six UHCI and two EHCI (High‐Speed 2.0) USB host controllers, with up to twelve USB ports
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