Abit SI-2PS User Manual page 35

BIOS Setup
Memory Frequency
This item displays the frequency of memory module you are using.
DRAM Timing Selectable
This item sets the optimal timings for the following four items, depending on the
memory module you are using. The default setting "By SPD" configures these four
items by reading the contents in the SPD (Serial Presence Detect) device. The
EEPROM on the memory module stores critical parameter information about the
module, such as memory type, size, speed, voltage interface, and module banks.
CAS Latency Time
This item controls the latency between the DRAM read command and the time that
the data becomes actually available.
Active to Precharge Delay
This item controls the number of DRAM clocks used for DRAM parameters.
DRAM RAS# to CAS# Delay
This item controls the latency between the DRAM active command and the read/write
command.
DRAM RAS# Precharge
This item controls the idle clocks after issuing a precharge command to the DRAM.
Delayed Transaction
When set to [Enabled], the PCI bus will be freed up when the CPU is accessing 8-bit
ISA cards. This will allow PCI and ISA buses to be used more efficiently and
prevents performance dropping on the PCI bus. This process normally consumes
about 50-60 PCI clocks without PCI delayed transaction. Leave this item to its default
[Disabled] setting when using ISA cards that are not PCI 2.1 compliant.
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User's Manual