HP ProLiant DL980 Specification page 38

QuickSpecs
Memory
NOTE: Memory configurations listed do not apply to "Factory Integrated Models".
HP ProLiant DL980 G7 Models
Memory Subsystem Architecture
Intel Xeon E7 Family, 7500 and 6500 series memory architecture is designed to take advantage of multiple stages of memory
interleaving to reduce latency and increase bandwidth.
Each Intel Xeon E7, 7500 and 6500 series processor contains two Memory Controllers as shown in the Processor/Memory interconnect
figure below. Each Memory controller has two Scalable Memory Interface (SMI) buses operating in lockstep where each SMI bus
connects to a memory buffer. The purpose of the buffer is to convert SMI to DDR3. Each buffer has two DDR3 channels and can support
up to four DIMMs for a total of eight DIMMs per cartridge.
The number of DIMMs or ranks does not affect memory frequency, but can affect memory bandwidth and performance. All
DIMMs will run at the highest possible frequency for a given processor.
DDR3 memory speed is a function of the processors QPI bus speed such that
Processors with a QPI speed of 6.4GT will run memory at 1066MHz
Processors with a QPI speed of 4.8GT will run memory at 800 MHz
DIMM Installation guidelines
Each memory cartridge can support up to 8 DIMMs, for a system total of 128 DIMMs. When installing DIMM modules in the Memory
Cartridge observe the following minimum guidelines:
UDIMMs are not supported
Minimum allowable configuration is 16 DIMMs (two DIMMs on each of the two cartridges connected to processor one through
four.
DIMMs must be installed as Quads (four DIMMs with identical characteristics). For configuration simplicity HP recommends using
identical part numbered DIMMs throughout when possible.
DIMM Quads MUST be populated in sequence by letter designation. Install DIMMs 1A and 8A on each cartridge first, followed by
DIMMs 3B and 6B on each cartridge, then DIMMs 2C and 7C, and finally DIMMs 4D and 5D last.
Maximum performance is achieved by balancing DIMM Quads by letter groupings across all memory cartridges. All 1A and 8A
DIMMs should be installed (preferably with the same size DIMMs in all memory cartridges across the entire system) first,
followed by the B DIMMs, C DIMMs and D DIMMs.
AMP modes Online Sparing and Memory Mirroring have further requirements beyond these listed here. Please refer to the user guide
for additional memory configuration requirements.
Memory Cartridge population guidelines
This server contains 8 memory cartridge slots within each processor memory drawer. Observe the following guidelines:
A memory cartridge must be installed in each slot.
To maximize performance distribute the total memory capacity evenly between all memory cartridges.
When operating the system in 40-bit address mode and installing 64x 16GB DIMMs (1TB total memory), the 64 DIMMs must be
spread evenly across all 16 memory cartridges, or some of the memory will not be recognized.
Memory configurations larger than 1TB require the use of 44-bit addressing mode.
Hemisphere mode
The Xeon EX architecture incorporates hemisphere mode, a high performance interleaving technology. Hemisphere mode allows
interleaving between the two processor memory controllers internal to each processor.
The DL980 G7 always uses Hemisphere mode. This requires that for each processor, the two memory cartridges attached to the
DA - 13708 North America — Version 38 — September 23, 2013
HP ProLiant DL980 Generation 7 (G7)
Page 38