Phy Event Counter; Table 81 Phy Event Counter Identifier - Hitachi Travelstar 2.5 inch SATA HTS722020K9A300 Oem Specification

If set to one, LBA Low is set to C4h if the unload is being executed or has completed successfully. It
is set to 4Ch if the unload was not accepted or has failed.
The NQ field (Byte 0 bit 7) indicates whether the error condition was a result of a non-queued or not.
If it is cleared, the error information corresponds to a queued command specified by the tag number
indicated in the TAG field.
The bytes 1 to 13 correspond to the contents of Shadow Register Block when the error was reported.
The Data Structure Checksum (Byte 511) contains the 2's complement of the sum of the first 511
bytes in the data structure. The sum of all 512 bytes of the data structure will be zero when the
checksum is correct.

Phy Event Counter

14.16.5
Phy Event Counters are a feature to obtain more information about Phy level events that occur on
the interface. The counter values are not retained across power cycles. The counter values are
preserved across COMRESET and software resets.
14.16.5.1
There are 2 mechanisms by which the host can explicitly cause the Phy counters to be reset. The
first mechanism is to issue a BIST Activate FIS to the drive. The second mechanism uses the Read
Log Ext command. When the drive receives a Read Log Ext command for log page 11h and bit 0 in
Feature register is set to one, the drive returns the current counter values for the command and then
resets all Phy event counter values.
14.16.5.2
Each counter begins with a 16-bit identifier. The following table defines the counter value for each
identifier.
For all counter descriptions, "transmitted" refers to items sent by the drive to the host and "received"
refers to items received by the drive from the host.
Bits 14:12 of the counter identifier convey the number of significant bits that counter uses. All
counter values consumes a multiple of 16-bits. The valid values for bit 14:12 and the corresponding
counter size are:
1h 16-bit counter
2h 32-bit counter
3h 48-bit counter
4h 64-bit counter
Identifier
(Bits 11:0)
000h
001h
009h
00Ah
00Bh
00Dh

Table 81 Phy Event Counter Identifier

14.16.5.3
The following table defines the format of the Phy Event counter data structure.
7K200 SATA OEM Specification
Counter Reset Mechanisms
Counter Identifiers
No counter value; marks end of counters in the page
Command failed due to ICRC error
Transfer from drive PhyRdy to drive PhyNRdy
Signature D2H register FISes sent due to a COMRESET
CRC errors within the FIS (received)
Non-CRC errors within the FIS (received)
Read Log Ext Log Page 11h
Description
112/173