Table of Contents
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Code
3Ah
3Ch
3Dh
41h
42h
45h
46h
47h
48h
49h
4Ah
4Bh
4Ch
4Eh
50h
51h
52h
54h
55h
58h
59h
5Ah
5Bh
5Ch
60h
62h
64h
66h
67h
68h
69h
6Ah
6Bh
6Ch
6Eh
70h
72h
76h
79
Beeps
Autosize cache
Advanced configuration of chipset
registers
Load alternate registers with CMOS
values
Initialize extended memory for
RomPilot.
Initialize interrupt vectors
POST device initialization
2-1-2-3
Check ROM copyright notice
Initialize I20 support
Check video configuration against
CMOS
Initialize PCI bus and devices
Initialize all video adapters in system
QuietBoot start (optional)
Shadow video BIOS ROM
Display BIOS copyright notice
Display CPU type and speed
Initialize EISA board
Test keyboard
Set key click if enabled
Enable USB devices
2-2-3-1
Test for unexpected interrupts
Initialize POST display service
Display prompt "Press F2 to enter
SETUP"
Disable CPU cache
Test RAM between 512 and 640 KB
Test extended memory
Test extended memory address lines
Jump to User Patch1
Configure advanced cache registers
Initialize Multi Processor APIC
Enable external and CPU caches
Setup System Management Mode
(SMM) area
Display external L2 cache size
Load custom defaults (optional)
Display shadow-area message
Display possible high address for UMB
recovery
Display error messages
Check for configuration errors
Check for keyboard errors
POST Routine Description
Chapter 4
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