Sharp CDC2900 - 3-CD Compact Stereo System Service Manual page 50

CD-C622/C2900
IC2 VHiLC78622N-1: Servo/Signal Control (LC78622NE) (2/2)
Pin
Terminal Name Input/Output
No.
47* SBSY Output
48* EFLG Output
49* PW Output
50* SFSY Output
51 SBCK Input
52* FSX Output
53 WRQ Output
54 RWC Input
55 SQOUT Output
56 COIN Input
57 CQCK Input
58 RES Input
59* TEST11 Output
60* 16M Output
61 4.2M Output
62 TEST5 Input
63 CS Input
64 TEST1 Input
Note: The same potential must be supplied to the power terminals (VDD, VVDD, LVDD, RVDD, XVDD).
In this unit, the terminal with asterisk mark (*) is (open) terminal which is not connected to the outside.
DEFI
Slice level
control
EFMIN
Sync detection
FSEQ
EFM demodulation
CLV+
C L V
Digital servo
CLV-
V/P
PW
Subcode division
SBCK
QCRC
SBSY
SFSY
CS
WRQ
C O M
Interface
SQOUT
CQCK
COIN
Servo commander
RWC
Sub-code clock sync signal output terminal.
C1, C2, single, double correction monitor terminal.
Sub-code P, Q, R, S, T, U, and W output terminal.
Sub-code frame sync signal output terminal. Falling occurs when the sub-code is in standby state.
Sub-code read clock input terminal. Schmidt input (When this terminal is not used, connect it to 0V.)
7.35 kHz sync signal (frequency-divided from crystal oscillation) output terminal.
Sub-code Q output standby output terminal.
Read/Write control input terminal. Schmidt input.
Sub-code Q output terminal.
Command input terminal from microcomputer.
Command input taking-in clock or sub-code taking-out (from SQOUT) clock input terminal.
Schmidt input
LSI resetting input terminal. When power is turned on, once "L" is set.
Output terminal for test. Use this terminal in open state (usually "L" output).
16.9344 MHz output terminal.
4.2336 MHz output terminal.
Input terminal for test. Pull-down resistor built-in. Be sure to connect this terminal to 0V.
Chip selection input terminal. Pull-down resistor built-in.
In noncontrol state connect this terminal to 0V.
Input terminal for test. Pull-down resistor is not provided. Be sure to connect this terminal to 0V.
2 K x 8 b i t
VCO colck oscillation
clock control
Flag processing of C1/C2
error detection and correction
XTAL system timing
General-use port
Figure 50 BLOCK DIAGRAM OF IC
– 50 –
Function
RAM address
generator
R A M
Interpolation mute
Bilingual
Digital
attenuator
X4 oversampling
digital filter
1 b i t D A C
L . P . F
generator
C2F
Digital OUT DOUT