5.6.2
Multiword data transfer
Figure 5.9 shows the multiword DMA data transfer timing between the device and the host
system.
DMARQ
DMACK-
DIOR-/DIOW-
Write data
DD0-DD15
Read data
DD0-DD15
Symbol
t0
Cycle time
tC
Delay time from DMACK assertion to DMARQ negation
tD
Pulse width of DIOR-/DIOW-
tE
Data setup time for DIOR-
tF
Data hold time for DIOR-
tG
Data setup time for DIOW-
tH
Data hold time for DIOW-
tI
DMACK setup time for DIOR-/DIOW-
tJ
DMACK hold time for DIOR-/DIOW-
tK
Continuous time of high level for DIOR-/DIOW-
Figure 5.9
tC
tI
tD
tG
tE
Timing parameter
Multiword DMA data transfer timing (mode 2)
C141-E099-01EN
t0
tJ
tK
tH
tF
Min.
Max.
120
—
70
—
5
20
10
0
5
25
Unit
—
ns
35
ns
—
ns
30
ns
—
ns
—
ns
—
ns
—
ns
—
ns
—
ns
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