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6-4 Logic Circuit Diagram
1
PDM1
SYNTH_LOCK
C100
10NF
A
SLEEP_N
IDLE_N
TRK_LO_ADJ
R112
100,1%
C125
C124
68NF
10NF
R130
10K
LNA_GAIN
RX_AGC_ADJ
R118
R119
1K
1K
C131
C132
4.7NF
10NF
Q_OFFSET
B
C133
100NF
R129
10K
I_OFFSET
V_RFTXD
C134
100NF
RX_QDATA0
RX_QDATA1
RX_QDATA2
RX_QDATA3
RX_IDATA0
RX_IDATA1
RX_IDATA2
RX_IDATA3
CX8_FM_CLK
PA_R0
R133
1.2K
C
TX_AGC_ADJ
R135
R136
1K
1K
C135
C136
V_MSMA
5.6NF
C137
10NF
100NF
C138
PA_ON
10NF
PA_IREF
CLOSE TO D5
Q_OUT_N
Q_OUT
I_OUT_N
I_OUT
* AUDIO : 150 -- 180
R140
180K
C140
100NF
C141
C142
12NF
R141
100NF
10K
R143
510K
R144
C143
12NF
10K
C144
R145
100NF
D
180K
C145
100NF
SPK_IN+
SPK_IN-
C148
1UF
R154
2.2K
C150
22NF
MIC+
C152
22NF
R167
2.2K
EAR_MIC+
H_TX_AUDIO
R163
30K
E
C159
100NF
H_RX_AUDIO
1
6-4
2
3
R102
4.7K
UIM_MSM_TXD
V_MSMP
UIM_RXD
RESOUT
RESOUT_N
R108
PON_RESET_N
510
C122
27PF
4
3
R111
18K
1
C126
2
27PF
OSC100
MC-146(32.768KHz,20ppm)
WDOG_EN
TCXO_CLK
YAMN1
R122
10K
B9
PDM2
C8
PDM1
C10
SYNTH_LOCK
A8
SLEEP_N
B7
IDLE_N
B11
TRK_LO_ADJ
B12
LNA_GAIN
C7
LNA_RANGE0
C9
R131
LNA_RANGE1
A11
RX_AGC_ADJ
B10
3.3K
Q_OFFSET
A10
I_OFFSET
D13
C_RX_QDATA0
C13
C_RX_QDATA1
B13
C_RX_QDATA2
A13
C_RX_QDATA3
B14
FM_RX_QDATA
B15
FM_RX_IDATA
C17
C_RX_IDATA2
C16
C_RX_IDATA3
A15
FM_RX_STB
A14
CX8_FM_CLK
U100
A9
PA_R0
D7
PA_R1
A12
MSM3100C
TX_AGC_ADJ
C11
PA_ON2
D6
PA_ON
NO : 100 -- 199
C4
DAC_IREF
A6
Q_OUT_N
B5
Q_OUT
B6
I_OUT_N
A7
I_OUT
F16
GND_RET
E15
CCOMP
G14
MICFBN
H17
MICINP
J17
MICOUTN
H16
MICOUTP
G16
MICINN
G15
MICFBP
L16
EAR10P
M17
EAR10N
G17
MICBIAS
J16
MIC1P
K17
MIC1N
H14
MIC2P
H15
MIC2N
K14
EAR20
J14
AUX1P
J15
AUX1N
C139
L17
AUX0P
22NF
K16
AUX0N
C153
22NF
C154
100NF
R164
C155
10K
100NF
2
3
4
5
V_MSMC
V_MSMP
V_MSMP
V_MSMC
R101
0
C101
C102
C103
C104
C105
C106
C107
C108
C109
C110
10NF
100NF
10NF
100NF
10NF
100NF
10NF
100NF
10NF
100NF
D9
K4
M15
E14
M4
P8
R107
8.2K
- IF USB IS NOT USED PLACE XTAL48_IN PIN TO GND
SBDT
SBCK
R109
SBST
91K,1%
ICHRG
C123
R113
BAT_ID
100PF
100K,1%
THERM_DET
TDO
TDI
TMS
TRST_N
TCK
TMODE
DP_TX_DATA
R121
DP_RX_DATA
10K
RTS
CTS
REED_SW
EL1_EN
SEND_END
D(0:15)
R12
D(0)
D0
U10
D1
D(1)
R11
D(2)
D2
T10
D(3)
D3
U9
D(4)
D4
P10
D(5)
D5
R10
D(6)
D6
T9
D(7)
D7
U8
D(8)
D8
R9
D(9)
D9
T8
D(10)
D10
U7
D(11)
D11
R8
D(12)
D12
T7
D(13)
D13
A(0:20)
U6
D(14)
D14
P7
D(15)
D15
A(0)
N16
A0
N15
A(1)
A1
U12
A(2)
A2
R13
A(3)
A3
T12
A(4)
A4
U11
A(5)
A5
T11
A(6)
A6
A(7)
P11
A7
R7
A(8)
A8
T6
A(9)
A9
U5
A(10)
A10
Q101
R6
A(11)
A11
R132
T5
A(12)
A12
100K
T4
A(13)
1
A13
A(14)
FROM_WP
R5
A14
U4
A(15)
A15
T3
A(16)
A16
2SA1576FRT106
R4
A(17)
A17
U3
A(18)
A18
U2
A(19)
A19
T2
A(20)
A20
N14
A(21)
GPIO(15)
A21
M14
SCAN(5)
GPIO(31)
A22
R15
ROM_CS1_N
ROM_CS1_N P4
ROM_CS2_N
P14
RAM_CS1_N
RAM_CS1_N
RAM_CS2_N N4
GPIO(37)
RAM_CS2_N
P6
GPIO(39)
GP_CS_N
LCD_CS2_N
P12
GPIO(40)
LCD_CS_N
LCD_CS_N
LCD_EN P13
GPIO(41)
EAR_DET
R14
RD_N
RD_N
P16
LWR_N
LWR_N
P15
HWR_N
L4
GND12
P9
GND11
L15
GND10
KEYSENS(0)
KEYSENS(1)
KEYSENS(2)
KEYSENS(3)
ON_SW_SENSE
UIM_PWR_EN_N
DTR
FROM_WP
UIM_RESET
R150
1K
PLL_EN
R151
1K
PLL_CLK
R152
1K
PLL_DATA
TCXO_EN
PS_HOLD
SCAN(0)
CD
SCAN(1)
SDA
SCL
MOTOR_EN
RI
SCAN(2)
AUDIO_CTRL
LED_EN
SCAN(3)
SCAN(4)
R162
1.2K
REED_SW
C158
10NF
Changed by
Date Changed
user12
Monday, November 12, 2001
4
5
6
7
V_MSMA
C111
C112
C113
C114
C115
C116
C117
C118
C119
100NF
10NF
100NF
10NF
100NF
10NF
100NF
10NF
100NF
D5
D10
F15
L14
V_RING
3
5
4
R114
10K
2
SLEEP_N
Q100
UMC5NTL
1
V_MSMP
V_MSMP
C127
100PF
C129
100NF
U110
DS42553
D(0:15)
A(1:21)
J5
VCCF
J6
V_MSMP
VCCS
A(1)
G2
H9
R124
100K
A0
CIOF
A(2)
F2
K6
R125
100K
A1
CIOS
R126
A(3)
E2
D6
A2
CE2S
A(4)
D2
RY/_BY E5
10K
A3
A(5)
F3
C6
A4
_WE
LWR_N
A(6)
E3
G8
A5
SA
A(7)
D3 A6
A(8)
C3 A7
A(9)
C7
A8
A(10)
E7
A9
A(11)
F7
A10
A(12)
C8
J3
D(0)
A11
DQ0
A(13)
D8
G4
D(1)
A12
DQ1
A(14)
E8
K4
D(2)
A13
DQ2
A(15)
F8 A14
H5
D(3)
DQ3
A(16)
D9
H6
D(4)
V_MSMP
A15
DQ4
A(17)
G9
K7
D(5)
A16
DQ5
A(18)
F4 A17
DQ6 G7
D(6)
A(19)
E4
DQ7 J8
D(7)
A18
A(20)
D7
K3
D(8)
A19
DQ8
A(21)
E6
H4
D(9)
A20
DQ9
J4
D(10)
DQ10 K5
D(11)
DQ11
J7
D(12)
DQ12
ROM_CS1_N
H2
H7
D(13)
ROM_CS1_N
_CEF
DQ13
RAM_CS1_N
J2
DQ14 K8
D(14)
RAM_CS1_N
_CE1S
RD_N
H3
H8
2
D(15)
RD_N
_OE
DQ15/A-1
C4
RAM_CS2_N
_LB
D4 _UB
A(0)
3
C5
G3
_WP/ACC
VSS1
D5
J9
PON_RESET_N
_RESET
VSS2
R134
100K
F10
NC
G1
A1 NC
NC
TCXO_CLK
A10
G10
NC
NC
B1 NC
L1
NC
B5
L5
NC
NC
B6
NC L6
NC
NC L10
B10
NC
C1 NC
M1
NC M10
E9
NC
NC
F1 NC
F9
NC
V_EAR
C149
100NF
3
8
+
1
EAR_DET
U170-1
-
2
4
TC75W56FK-TE12L
5
+
7
SEND_END
U170-2
-
6
TC75W56FK-TE12L
EAR_REF
V_MSMP
Engineer
H.G.KIM
U199
A3210ELH
Drawn by
2
VCC 1
C.K.KIM
OUT
GND
C156
R&D CHK
TITLE
3
100NF
C157
100NF
DOC CTRL CHK
MFG CTRL CHK
REV
Time
QA CHK
06
5:05:06 pm
6
7
8
V_EAR
3.0TCXO
R148
0
A
V_MSMP
U131
1
8
VCC
A0
7
2
R146
WP
A1
100K
6 SCL
3
A2
SCL
5
4
SDA
GND
SDA
R153
1K
AT24C256-10UI-2.7-T.R
B
V_TCXO
U140
TC7S04FU(TE85L)
C120
100NF
5
1
VCC
NC
2
IN
C
4
3
OUT
GND
C121
C160
10NF
1NF
TCXO_IN
R110
100K
V_EAR
R155
C151
100K
47NF
R156
510
D
V_EAR
R161
100K
EAR_MIC+
R165
100K
SAMSUNG
Size
E
D
SCH-A399_REV2.0-MSM
Drawing Number
Sheet1
8
Circuit Diagram
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