Samsung SGH-E330 Service Manual page 8

Circuit Description
8. Memory
Signals in the OM6359 enable two memories. They use only one volt supply voltage, VDD3 in the PCF50601. This
system uses Samsung's memory, KBB06A500M-T402. It is consisted of 128M bits flash NOR memory and 128M bits
flash NAND memory and 64M bits SCRAM. It has 16 bit data line, HD[0~15] which is connected to OM6359 and
MV317S. It has 26 bit address lines, HA[1~26]. CS_NAND and NCSRAM signals are chip select. Writing process,
HWR_N is low and it enables writing process to flash memory and SRAM. During reading process, HRD_N is low and
it enables reading process to flash memory and SRAM. Each chip select signals in the OM6359 select memory among 2
flash memory and SCRAM. Reading or writing procedure is processed after HWR_N or HRD_N is enabled. Memories
use reset, which is VDD3 delay from PCF50601. HA[25] signal enables lower byte of SRAM and HA[26] signal enables
higher byte of SRAM.
9. OM635
9
OM6359 is consisted of ARM core and DSP core. It has 8x 1Kwor d on- c hip pr ogr a m/ da ta RAM, 55 Kwor ds
on- c hip pr ogr am ROM in the DSP. It has 4K*32bits ROM and 2K*32bits RAM in the ARM core. DSP is consisted
of KBS, JTAG, EMI and UART. ARM core is consisted of EMI, PIC(Programmable Interrupt Controller),
reset/power/clock unit, DMA controller, TIC(Test Interface Controller), peripheral bridge, PPI, SSI(Synchronous Serial
Interface), ACC(Asynchronous communications controllers), timer, ADC, RTC(Real-Time Clock) and keyboard interface.
KBIO(0:7), address lines of DSP core and HD[0~15]. HA[1~26], address lines of ARM core and HD[0~15], data lines of
ARM core are connected to memory, YMU762C. MV317S(Camera DSP Chip) controls the communication between ARM
core and DSP core.
CS_NAND, NCSRAM, NCSFLASH in the ARM core are connected to each memory. HWR_N and HRD_N control the
process of memory. External IRQ(Interrupt ReQuest) signals from each units, such as, PMU need the compatible process.
KBIO[0~7] receive the status from key and RXD0/TXD0 are used for the communication using data link
cable(DEBUG_DTR/RTS/TXD/RXD/CTS/DSR).
It has JTAG control pins(TDI/TDO/TCK) for ARM core and DSP core. It receives 13MHz clock in CKI pin from
external TCXO. ADC(Analog to Digital Convertor) part receives the status of temperature, battery type and battery voltage.
10. TOH2600DGI4KRA(26MHz)
This system uses the 26MHz TCXO, TOH2600DGI4KRA, SEM. AFC control signal from OM6359 controls frequency
from 26MHz x-tal. The clock output frequency of UAA3536 is 13MHz. This clock is connected to OM6359, YMU762C.
11. Camera DSP(MV317S)
Tiger is an Integrated circuit for mobile phone camera. This structure will allow effectiveness for large
data management and significantly reduces main processor will get burden.
In hence, Tiger will allow the user to be able to display to LCD direct without burdening the main
processor. It also allows to have various kinds of display size on the LCD and snapshot for Jpeg. Digital
effect will also be executed on real time base resulting Tiger as being a video co- processor in the
mobile platform. Also,an
interchange the data with Tiger. As the additional 8Mbit is usable except 2Mbit buffer embedded in Tiger, the diverse UI
data processing which is not a bur de n to the CPU is ava ila ble . JPEG e nc ode r a nd de c ode r a r e ba s e line
ISO/IEC 10 918 - 1 JPEG complia nc e (DCT - ba s e d). JPEG de c ode r s uppor ts YUV444, YUV422, YUV420 a nd
YUV411 for mat s ta nda r d JPEG image .
i80 type processor' s 16bit parallel interface of Tiger makes it available for the CPU to
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