Cache Data Integrity; Data Check Flow On Instruction Fetch; Data Check Flow On Load Operations - NEC uPD98502 User Manual

2.7.6 Cache data integrity

Figures 2-72 to 2-86 shows checking operations for various cache accesses.
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CHAPTER 2 V
Figure 2-72. Data Check Flow on Instruction Fetch
Start
Tag Check
Miss
Refill (See
Figure 2-85)
Data Fetch
END
Figure 2-73. Data Check Flow on Load Operations
Start
Tag Check
Miss or
Invalid
V bit, W bit
V = 1 ( valid ) and
W = 1 (dirty)
Write-back and
Refill (see
Figure 2-86)
Data Load to
Register
END
Preliminary User's Manual S15543EJ1V0UM
4120A
R
Hit
Hit
V = 0 (invalid)
or
W = 0 (clean)
Refill (see
Figure 2-85)