Post Codes - Acer Aspire M5-481PT Service Manual

Acer aspire m5-481t, pt, and tg notebook service guide
Hide thumbs Also See for Aspire M5-481PT:
Table of Contents

Advertisement

Post Codes

The following are the InsydeH2O™ Functionality POST code tables. The components of the
POST code table includes: SEC phase, PEI phase, DXE phase, BDS phase, CSM functions,
S3 functions and ACPI functions.
Post Code Range
Phase
SEC
PEI
DXE
BDS
SMM
S3
ASL
PostBDS
InsydeH2ODDT™ Reserve
OEM Reserve
Reserved
SEC Phase Post Code
Functionality Name
(Include\PostCode.h)
SEC_SYSTEM_POWER_ON
SEC_BEFORE_MICROCODE_PATCH
SEC_AFTER_MICROCODE_PATCH
SEC_ACCESS_CSR*
SEC_GENERIC_MSRINIT*
SEC_CPU_SPEEDCFG*
SEC_SETUP_CAR_OK
SEC_FORCE_MAX_RATIO*
SEC_GO_TO_SECSTARTUP
Troubleshooting
POST Code Range
0x01 - 0x0F
0x70 - 0x9F
0x40 - 0x6F
0x10 - 0x3F
0xA0 - 0xBF
0xC0 - 0xCF
0x51 – 0x55
0xE1 – 0xE4
0xF9 – 0xFE
0xD0 – 0xD7
0xE8 – 0xEB
0xD8 – 0xE0
0xE5 – 0xE7
0xEC – 0xF8
Phase
SEC
SEC
SEC
SEC
SEC
SEC
SEC
SEC
SEC
Post
Description
Code
01
CPU power on and switch to
Protected mode
02
Patching CPU microcode
03
Setup Cache as RAM
04
PCIE MMIO Base Address
initial
05
CPU Generic MSR
initialization
06
Setup CPU speed
07
Cache as RAM test
08
Tune CPU frequency ratio to
maximum level
09
Setup BIOS ROM cache
0
4-15

Advertisement

Table of Contents
loading

This manual is also suitable for:

Acer m5 481Acer m5 481gAcer m5 481tAcer m5 481tg

Table of Contents