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Ultra DMA Timing
Ultra DMA Timing
Ultra DMA Timing
Ultra DMA Timing
Ultra DMA Timing
T IM IN G PARAMET ERS (all tim es in nanoseco nds )
t
Cycle Time (from STROB E edge to STROBE ed ge)
CYC
t2
Two cycle time ( fro m ris ing edge to next r is ing edge or
CYC
from falling edge to next fal li ng edge of STROBE )
t
D a ta s etup time (at r ec ipi ent)
DS
t
D ata hold time (at r ec ipi ent)
DH
t
D ata valid setup time at sender (time from data bus bei ng
DVS
valid unti l STROB E edge)
t
Data valid hold time at sender (time from STROBE e dge
DVH
until data may go invali d)
t
Fi rs t STROBE (time for devi ce to send fi rst STROBE)
F S
t
Li mited i nterlock time (time allo wed between an acti on by
L I
one agent, either host or device, and the following acti on
by the othe r agent)
t
Inter lock ti me wi th mini mum
ML I
t
Unli mi ted inte rlock ti me
UI
t
Maxim um ti me allowed for outputs to r el ease
AZ
t
Mi nimum delay time re quired for output drivers turni ng on
ZAH
(from releas ed state )
t
Z AD
t
Envelope ti me (all control si gnal transi tions are within the
ENV
D MACK envelope by thi s much ti me)
t
STROBE to D MA RDY (re sponse ti me to ensure the
SR
synchr onous pause case when the rec ip ient is pausing)
t
Ready-to-final -STROBE ti me (no more STROBE edges
RF S
ma y be sent thi s long after recei ving D MARDY- negati on )
t
Ready-to-p ause ti me (time unti l a reci pient may assume
RP
that the sender has paused after negation of D MARDY-)
t
Pull-up time before allowing IORD Y to be r eleas ed
IORDYZ
t
Mi nim um time devi ce shall wait b efor e dr iving IORDY
Z IORD Y
t
Setup and hold ti mes before asser ti on and negati on of
ACK
DMA C K-
t
Time from STROB E edg e to STOP assertion when the
SS
sender is stopping
DMARQ
(device)
DMACK-
(host)
STOP
(host)
HDMARDY-
(host)
DSTROBE
(device)
DD(15:0)
DA0, DA1, DA2,
CS0-, CS1-
MODE 0
MODE 1
MIN
MAX
MIN
112
73
230
153
15
10
5
5
70
48
6.2
6.2
0
230
0
0
150
0
20
20
0
0
10
20
20
0
0
20
70
20
50
75
160
125
20
0
0
20
20
50
50
t
UI
t
t
ACK
ENV
t
ZAD
t
t
ACK
ENV
t
ZAD
t
ZIORDY
t
AZ
t
ACK
Figure 5 - 4
Initiating an Ultra DMA Data In Burst
MODE 2
MODE 3
MAX
MIN
MAX
MIN
MAX
MIN
54
39
115
86
7
7
5
5
31
20
6.2
6.2
200
0
170
0
130
150
0
150
0
100
20
20
0
0
10
10
10
20
20
0
0
70
20
70
20
55
30
20
NA
70
60
60
100
100
20
20
20
0
0
20
20
50
50
t
FS
t
FS
t
t
VDS
DVH
AT INTERFACE DESCRIPTION
MODE 4
MODE 5
MAX
MIN
MAX
25
16.8
57
38
5
4
5
4.6
6.7
4.8
6.2
4.8
0
120
0
90
0
100
0
75
20
20
0
0
10
10
20
20
0
0
20
55
20
50
NA
NA
60
50
100
85
20
20
0
0
20
20
50
50
5 – 5
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