3.1
Introduction
This chapter describes the processor/memory subsystem. This systems support the AMD
Phenom, Athlon, and Sempron processor families. As shown in Figure 3-1, these processors use
an integrated DDR2 memory controller and communicate with the chipset through the
HyperTranport interface (I/F).
Figure 3-1. Processor/Memory Subsystem Architecture
This chapter includes the following topics:
■
AMD processors (3.2)
■
Memory subsystem (3.3)
Technical Reference Guide
Processor/Memory Subsystem
AMD Processor
Core(s)
DDR2
Controller
L2 Cache
HyperTransport I/F
North Bridge
www.hp.com
XMM1
DIMM
Channel A
Channel B
DIMM
XMM2
XMM3
DIMM
DIMM
XMM4
3
3-1