Circuit Description - ViewSonic VE910B Service Manual

4. Circuit Description

A. DC-DC Converter
This brick convert is the 110-220AC input voltage to 12V AND 5V output for invert use and
panel use and system controller use .
It consists of a PWM IC (FP5001, I804), flywheel diode (MS22,D812), buck choke (L812)
and capacitor C817.
5V Out put at 5,6 pin
VCC 12V In put at L801,L812 pin
B. Scaling controller
The ADC is to convert RGB analog signal to digital signal that scaling chip can acknowledge.
The HSYNC input receives a logic signal and provides the frequency reference for pixel clock
generation.
The scaling IC is to converts the input signal ranging from VGA to SXGA into SXGA
resolution that panel can acknowledge.
The scaling IC is to converts the input signal ranging from VGA to SXGA into SXGA
resolution that panel can acknowledge.
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GENERAL DESCRIPTION
The TSU16AS is total solution graphics processing IC for LCD monitors with panel
resolutions up to SXGA. It is configured with a high-speed integrated triple-ADC/PLL, a high
quality display processing engine, and an integrated output display interface that can support
LVDS panel interface format. To further reduce system costs, the TSU16AS also integrates
intelligent power management control capability for green-mode requirements and
spread-spectrum support for EMI management.
The TSU16AS incorporates the world's first coherent oversampled RGB graphics ADC in a
monitor controller system1. The oversampling ADC samples the input RGB signals at a
frequency that is much higher than the signal source pixel rate. This can preserve details in the
video signal that ordinarily would be lost due to input signal jitter or bandwidth limitations in
non-oversampled systems.
The TSU16AS also incorporates a new Dynamic Frame Rate (DFR) generator2 for the digital
output video to the display panel that preserves the advantages of a fixed output clock rate,
while eliminating the output end of frame short-line.
1,2 Patent Pending
PIN DESCRIPTION
CPU Interface
Pin Name Pin Type Function Pin
HWRESET Schmitt Trigger Input w/
5V-tolerant
Hardware reset; active high 5
INT Output CPU interrupt; 4mA driving strength 27
AD3 I/O w/ 5V-tolerant DDR direct bus AD3; 4mA driving strength 4
AD2 I/O w/ 5V-tolerant DDR direct bus AD2; 4mA driving strength 1
AD1 I/O w/ 5V-tolerant DDR direct bus AD1; 4mA driving strength 2
AD0 I/O w/ 5V-tolerant DDR direct bus AD0; 4mA driving strength 3
ALE I w/ 5V-tolerant DDR direct bus ALE; active high 24
WRZ I w/ 5V-tolerant DDR direct bus WRZ; active low 25
RDZ I w/ 5V-tolerant DDR direct bus RDZ; active low 26
Analog Interface
Pin Name Pin Type Function Pin
HSYNC Schmitt Trigger Input w/
5V-tolerant
Analog HSYNC input 8
VSYNC Schmitt Trigger Input w/
5V-tolerant
Analog VSYNC input 9
REFP Internal ADC top de-coupling pin 22
REFM Internal ADC bottom de-coupling pin 23
RINP Analog Input Analog red input 19
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VE910/b