Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 3 REV 2.3 Manual page 339

4.4.1.2 Integer Load – Increment by Register
40
M2
Instruction
ld1.ldhint
ld2.ldhint
ld4.ldhint
ld8.ldhint
ld1.s.ldhint
ld2.s.ldhint
ld4.s.ldhint
ld8.s.ldhint
ld1.a.ldhint
ld2.a.ldhint
ld4.a.ldhint
ld8.a.ldhint
ld1.sa.ldhint
ld2.sa.ldhint
ld4.sa.ldhint
ld8.sa.ldhint
ld1.bias.ldhint
ld2.bias.ldhint
ld4.bias.ldhint
ld8.bias.ldhint
ld1.acq.ldhint
ld2.acq.ldhint
ld4.acq.ldhint
ld8.acq.ldhint
ld8.fill.ldhint
ld1.c.clr.ldhint
ld2.c.clr.ldhint
ld4.c.clr.ldhint
ld8.c.clr.ldhint
ld1.c.nc.ldhint
ld2.c.nc.ldhint
ld4.c.nc.ldhint
ld8.c.nc.ldhint
ld1.c.clr.acq.ldhint
ld2.c.clr.acq.ldhint
ld4.c.clr.acq.ldhint
ld8.c.clr.acq.ldhint
3:330
37 36 35 30 29 28 27 26
4 m x hint x
6
4 1 6 2 1
Operands
r = [r ], r
1 3 2
20 19 13 12
r r
3 2
7 7
Extension
Opcode
m x
4 1 0
6 5
r qp
1
7 6
x hint
6
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10
11
See Table 4-39
12
on page 3:328
13
14
15
16
17
1B
20
21
22
23
24
25
26
27
28
29
2A
2B
Volume 3: Instruction Formats
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