Toshiba BDX2500KU Service Manual page 26

IC5201 NT5CB64M16AP/NT5CB128M8AN/NT5CB256M4AN - 2
Input / Output Functional description
Symbol Type
RESET Input
NC
VDDQ Supply
VDD Supply
VSSQ Supply
VSS Supply
VREFCA Supply
VREFDQ Supply
ZQ Supply
Note: Input only pins (BA0-BA2,A0-A13,RAS,CAS,WE,CS,CKE,ODT, and RESET) do not supply termination.
DDR3 SDRAM Addressing
Configuration
# of Bank
Bank Address
Auto precharge
BL switch on the fly
Row Address
Column Address
Page size
Note:
Page size is the number of data delivered from the array to the internal sense amplifiers when an ACTIVE command
is registered. Page size per bank, calculated as follows:
Page size = 2 COLBITS * ORG / 8
COLBITS = the number of column address bits
ORT = the number of I/O (DQ) bits
Active Low Asynchronous Reset: Reset is avtive when RESET# is LOW, and
inactive when RESET# is HIGH. RESET# must be HIGH during normal operation.
RESET# is a CMOS rail to rail signal wigh DC high and low at 80% and 20% of VDD,
I,e, 1.20V for DC high and 0.30V.
No Connect: No internal electrical connection is present.
DQ Power Supply: 1.5V ± 0.075V
Power Supply: 1.5V ± 0.075V
DQ Ground
Ground
Reference voltage for CA
Reference voltage for DQ
Reference pin for ZQ collbration.
NT5CB256M4AN
8
BA0 - BA2
A10 / AP
A12 / BC
A0 - A13
A0 - A9,A11
1KB
5-2
Function
NT5CU128M8AN
8
BA0 - BA2
A10 / AP
A12 / BC
A0 - A13
A0 - A9
1KB
NT5CB64M16AP
8
BA0 -BA2
A10 / AP
A12 / BC
A0 - A12
A0 - A9
2KB