Exit Menu - TYAN THUNDER N3600B Manual

Feature
NorthBridge Chipset Configuration
Memory Timing
Parameters
Memory CLK
CAS Latency (Tcl)
RAS/CAS Delay (Trcd)
Min Active RAS (Tras)
Row Precharge Time
(Trp)
RAS/RAS Delay (Trrd)
Row Cycle (Trc)
Asynchronous Latency
Option
CPU Node 0
Reports CPU1 or CPU2 DRAM timing.
CPU Node 1
It shows the clock frequency of the
Read only
installed SDRAM.
This controls the timing delay (in clock
Read only
cycles) before SDRAM starts a read
command after receiving it.
When DRAM is refreshed, both rows
and columns are addressed
separately. This setup item allows you
to determine the timing of the transition
Read only
from RAS (row address strobe) to CAS
(column address strobe). The less the
clock cycles, the faster the DRAM
performance.
This setting allows you to select the
number of clock cycles allotted for the
RAS pulse width, according to DRAM
Read only
specifications. The less the clock
cycles, the faster the DRAM
performance.
This item controls the number of cycles
for Row Address Strobe (RAS) to be
allowed to precharge. If insufficient
time is allowed for the RAS to
Read only
accumulate its chage before DRAM
refresh, refresh may be incomplete and
DRAM may fail to retain data. This
item applies only when synchronous
DRAM is installed in the system.
Auto uses hardware compensation
values. Other values add to or subtract
Read only
from hardware generated value.
Recommended setting is Auto.
Bits 7-4. RAS#-active to RAS#-active
Read only
or auto refresh of the same bank.
Bits 3-0. This filed should be loaded
with a 4-bit value equal to the
Read only
maximum asynchronous latency in the
DRAM read round-trip loop.
70
http://www.tyan.com
Description