The Transition From Megahertz To Gigatransfers - Compaq BL10e - HP ProLiant - 512 MB RAM Update Manual

ISS Technology Update

The transition from Megahertz to Gigatransfers

Traditional front side bus architecture
The front side bus (FSB) has been the traditional interconnect between processors and the system chipset. The FSB is
unidirectional and it is shared by all of the devices (processors and chipset) that are attached to it. The FSB in Intel processor-
based systems is clocked at a frequency (speed) of 266 MHz, 333 MHz or 400 MHz. However, the processors and chipsets
deliver a new set of 64 bits onto the bus at four times per clock cycle, referred to as ―quad-pumping.‖ Therefore, a more
accurate way to express the speed of the bus is to use the number of data transfers per second. For example, a quad-pumped
400-MHz bus delivers 4 transfers/clock cycle × 400 million cycles/sec, or 1600 Megatransfers/sec. This number is sometimes
incorrectly quoted as megahertz (MHz).
Point-to-Point link-based architectures
AMD Opteron ™ based HP ProLiant servers and Intel
have eliminated the FSB in favor of bi-directional, point-to-point links that connect the processors to each other and each
processor to the chipset. These links (the AMD HyperTransport™ and the Intel
independently send data to, or receive data from, another processor or the chipset.
Both the AMD HyperTransport and Intel QuickPath Interconnect (QPI) have bi-directional links that are double-pumped (two data
transfers per clock cycle). The AMD HyperTransport 3.1 has scalable links up to 16 bits (2 bytes) wide each, and it supports
data rates up to 6.4 GT/s in each direction. The Intel QPI also uses a maximum of 16 bits per link to transfer data, and it
currently supports data rates up to 6.4 GT/s in each direction.
Bandwidth – the ultimate yardstick
To effectively compare the unidirectional, shared FSB with bi-directional, point-to-point links, we need to use a common metric—
the theoretical maximum bandwidth. Bandwidth is calculated by multiplying the data rate by the width of the bus or link.
For example, the bandwidth of the 400-MHz, quad-pumped FSB mentioned earlier is calculated as follows:
Maximum bandwidth = (1600 MT/s x 8 bytes per transfer) / 1000 = 12.8 GB/s
In the case of the AMD HyperTransport 3.1 and Intel QPI, bandwidth is calculated is as follows:
Maximum bandwidth
Additional resources
For additional information on the topics discussed in this article, visit:
Resource
Introduction to Intel QuickPath
Technology
HyperTransport (HT) Consortium
homepage
= 6.4 GT/s x 2 bytes per transfer x 2 links per interconnect
= 25.6 GB/s (12.8 GB/s maximum in each direction)
URL
www.intel.com/technology/quickpath
www.hypertransport.org
® Microarchitecture Nehalem-based HP ProLiant Generation 6 (G6) servers
®
Volume 8, Number 4
QuickPath Interconnect) allow each processor to
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