Outline Of The Product - Pioneer DVR-5100H-S Service Manual

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7.4 OUTLINE OF THE PRODUCT
i Main newly developed technologies
1. Pickup
The pickup supports quadruple-speed recording for the DVD-
R/RW.
A liquid-crystal tilt servo system is adopted for the pickup.
2. Recording-signal-processing LSI
* UPD3320GC (DRIVE Assy: IC 101)
The recording-signal-processing module of conventional models
consists of two chips, but this has been integrated into a
single newly developed recording-signal-processing LSI, enabling
stable performance and cost reduction.
3. AV-signal-processing LSI
* M65672WG-B (MAIN Assy: IC 1001)
The AV-signal-processing module of conventional models
consists
of eleven chips, but this has been integrated into a single
newly developed AV-signal-processing LSI, enabling large-scale
cost reduction while maintaining the conventional functions. In
the new LSI, all the basic functions necessary fora DVD
recorder have been integrated. Like conventional models, this
model is designed to support multitasking. The main functions
are as follows:
¢ 3-D Y/C separation
* Video decoding
¢ Frame TBC
¢ MPEG video encoding
* Dolby Digital Consumer Encoding
* ATA/ATAPI I/F (2 ch)
* Main CPU (32-bit RISC, 54 MHz)
¢ Graphics engine (OSD, scaling, mixing)
¢ MPEG video decoding
* Audio decoding (AC-3, MPEG)
* Video encoding
* Progressive conversion
¢ Audio I/F
* 3-D DNR for playback
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B) MAIN ASSY
4. DV-signal-processing LSI
The DV-signal-processing LSI consists of the following two
chips:
* UPD72862AGB-SEU (MAIN Assy: IC5101)
A 400-Mbps two-port PHY LSI in compliance with the
TEEE1394a-
2000 standards
* UPD72893AGD-LML (MAIN Assy: IC5202)
An EEE1394 link controller LSI having DV (digital video)
encoding/decoding functions. Encoding/decoding of digital video
signals in compliance with the SD specifications (NTSC/PAL) of
the DV standard is supported. The 32-bit RISC CPU is built in
for controlling the IEEE1394 bus and sending/receiving AV/C
commands.
Ic5202
(Side A)
IC1001
(SIDE B)
Fig.1 MAIN Assy