Bq20Z70/Bq29330 Circuit Module Schematic; Circuit Module Physical Layouts And Bill Of Materials - Texas Instruments bq20z70EVM-001 SBS 1.1 User Manual

bq20z70/bq29330 Circuit Module Schematic

2.2 Pin Descriptions
3 bq20z70/bq29330 Circuit Module Schematic
This section contains information for modifying and choosing a precharge mode for
bq20z70/bq29330/bq29412 implementation.
3.1 Schematic
The schematic follows the bill of materials in this user's guide.
3.2 Choosing Particular Precharge Mode
The chipset supports both a charger that has a precharge mode and one that does not. The EVM by
default supports a charger that does not have a precharge mode. This is configured by grounding the
PMS pin with a resistor. R12 and Q2 are used as the precharge current path in order to sustain sufficient
Pack+ voltage when the battery voltage is too low to power up the bq29330 IC.
If the charger has a precharge function, R12 and FET Q2 are not used. The PMS pin must be pulled high
to disable ZVCHG output. The charge FET Q1 is used as the precharge FET, and the charger must
control the precharge current and voltage.
Note: The configuration at PMS pin is a hardware level control. Once the bq20z70 is up and running, the
firmware may change the precharge settings. Please refer to bq20z70 datasheet for further information.
3.3 Testing Fuse-Blowing Circuit
To prevent the loss of board functionality during the fuse-blowing test, the actual chemical fuse is not
provided in the circuit. FET Q4 drives TP3 low if a fuse-blow condition occurs; so monitoring TP3 can be
used to test this condition.
4

Circuit Module Physical Layouts and Bill of Materials

This section contains the board layout, bill of materials, and assembly drawings for the bq20z70/ bq29330/
bq29412 circuit module.
Note:
4 bq20z70EVM-001 SBS 1.1 Impedance Track™Technology
Enabled Battery Management Solution Evaluation Module
Downloaded from Elcodis.com electronic components distributor
PIN NAME
1N
1P
2P
3P
4P
SMBC
SMBD
VSS
PACK–
SYS PRES
PACK+
For the battery pack designer: D3 is not recommended, and should be shorted out if the
DSG FET does not have built-in zener diode protection.
DESCRIPTION
–ve connection of first (bottom) cell
+ve connection of first (bottom) cell
+ve connection of second cell
+ve connection of third cell
+ve connection of fourth (top) cell
Serial communication port clock
Serial communication data port
Pack negative terminal
Pack negative terminal
System present pin (if low, system is present)
Pack positive terminal
SLUU242A – May 2006 – Revised June 2006
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