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1-2. THE SONY LDP-1000 INTERFACE
As mentioned before, the LDP-1000 has a microprocessor system
control in which the circuits are almost the same as in regular com-
puters.
·
The major interface component of the LDP-1000 is an I.C. chip, des-
ignated as· an 8251 by Intel, and called a universal synchronous/asyn-
chronous receiver transmitter, or USART for short. This integrated cir-
cuit can be programmed to handle either synchronous or asynchronous
serial 1/0 with variable word length, clock division, ratios, number of
stop bits, status of parity check, transmit control, and receive control.
In LDP-1000, the 8251 is progammed as listed below.
Mode
Word
length
Transmit Clock
Parity Check
Stop Bit
LDP-1000 initialize
format.
Initialize flow chart
Reset
Moda
1st Sync
2nd Sync
Command
y
Asynchronous
BBit
16
times of
baud rate
None
1, 1 ½.
2 (selectable)
Mode instruction
D7
D6
D5
I
S2
I
S1
I
EP
N
N
I
Stop bit
Data
........
1
N
0
1
5
When the 8251 is first powered up, or after it is reset, 8251 logic as-
sumes a mode select command mode.
If
the mode select command spe-
cifies asynch~onous mode, then logic switches to expecting control
select modes (command). This persists until the 8251 is reset, or a special
control select is output forcing the choice back to mode select.
1-3.
LDP-1000 EXTERNAL COMPUTER
INTERFACE CONNECTIONS
External CPU
LDP-1000
FG
1
1
frame ground
TxD
2
..
.
2
transmitted data
RxD
3
~
3
received data
RTS
: ::J
c:
request to s8nd
CTS
clear to send
DSR
6
=====--=====
6
data set ready
DTR
20
20
data terminal ready
7
7
signal ground
Set DIP SW on MP-11 board.
0
D4
D3
D2
PEN
I
L2
L1
I
•
0
1
1
1
1½
2
D1
B2
,.
DO
B1
I
0
0
0
0
r""'7
r 9
r"""'9
S1
r·· ----,
I
i
L-----,.1
Note: SW's 6 and 7 are
not used.
LBau:rete
0
1
0
1
1
,i1
x16
x64
. Word length (bit)
0
1
0
1
0
0
1
1
5
6
7
8
1-Enable
0-Disable
1-Even
0-0dd
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