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As Figure 3-44 indicates, MFM Clock is writ-
ten whenever there is a decode of
00
along
wi th Not WZite Clock..
The clock is advanced
or retarded if there is. a simultaneous early
or late decode (1000, etc.).
The MPH Data
signal is written whenever there is a decode
of
-1-
along with write Clock being
trwr.
Data may
also
be
on
time,
advanced, or re
tarded.
Write Driver Circuits
The compensated Write data is sent to the
Write Drive Circuits where it is applied to
a differential receiver.
The receiver is
enabled by the write Enable signal which is
true only when
the
drive logic indicates a
safe write condition.
If this signal is
true the data passes through the receiver
to the Write Toggle Pr.
The output of the Write T09gle
FF
is pro-
cessed by a symetry restore circuit.
This
discrete circuit
(OEL)
restores symetry
that may have been lost when the data was
transmitted from the Write Compensation
circuits (located in the logic chassis)
to
the driver circuits (located on the check).
Refer to section 5 of this manual (Discrete
Circuits) for a description of this circuit.
The magnitude of the Write current flowing
in the heads is controlled as a function
of cylinder address (this is referred to as
Write Current Zoning).
These zones are as
follows:
• 0-127
• 128-255
• 256-511
• 512-1022
Write current amplitude is reduced at each
zone boundary from outer to inner tracks.
Figure 3-45 shows the Write Driver circuits
and its associated timing.
Writing Address Marks
The drive writes an address mark
(AM)
while
Data Modifier Line is up.
This prevents the
output of the write compensation circuit
(Figure
3-44)
from being applied to the write
driver chain {Fiqure
3-40}.
Current
~
to flow through the write coil but, since
there is no current reversal, no flux trans-
itions occur.
Therefore, the read circuit.
cannot recognize the constant flux as usable
information.
The controller raises Data Modifier Line
while the drive is writing the zeros gap. At
the next
8
Bits Processed (a byte has just
been written) :
3-88
1.
Not Address Mark Enable FF clears (Fig-
ure 3-44).
All
MFM
clock/data pulses
are unconditionally inhibited.
2.
Fault Enable
A
FF sets, inhibiting
Enable Fault (Figure 3-36).
During
normal write operations, a lack of
write driver transitions will set CUr-
rent Fault.
This condition is occur-
ring during Data
""'1 tier L.i.ne but it is
normal.
The fault detection must,
therefore, be disabled.
Data continues to be inhibited as long as
Data Modifier Line remains up.
The Serial
Read In/Serial Write Out dialog continues,
data is -accepted- into SERDES, but it is
not gated to the write driver.
After the first
AM
byte is written,
8
Bits
Processed sets Fault Inhibit
8 FF.
Then,
Fault Inhibit A FP clears at the next 8 Bits
Processed: Not Address
Mark
Enable FF sets
to aq.ain permit data to
be
written.
Fault
Inhibit B
PP
waits for one more byte: there-
fore, a current Fault cannot be generated
during the first byte (zeros) following the
AM
bytes.
Current Fault is generated it
Data Modifier Line is up for more than three
bytes.
Write Fault Detection
Extensive monitoring circuits warn the con-
troller of data transfer errors or hardware
failures.
Either condition will raise FLT
to the controller.
Hardware failures will
set the Pack Unsafe FF: the CHECK indicator
lights and writinq is terminated.
Refer to Table
3-3
(Commands) for an explan-
ation of these error conditions.
Events
that can be considered as related to write
errors are:
Byte
ill
!!!!!.
OS1
2 0
Data Parity Error
DSl
21
Transfer Timinq Error
DSl
22
Protect Violation
OSl
24
State Violation
OSl
27
Command Parity Error
DS2
24
NO
or Multiple Head
Selection
OS2
2
5
Loss of AC Write Current
OS2
2
6
Write Current Without
Write Command
DS2
27
Write Command Without
Write Current
DSS
2°
write and Read
83318200
A
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