Aiwa NSX-MT70 Service Manual page 72

Compact disc stereo cassette receiver
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IC, CXD2540Q
Pin No.
Pin Name
V/O
Description
1
FOK
I
Focus OK input. Used for SENS output and the servo auto sequencer.
2
FSW
O
Spindle motor output filter switching output.
3
MON
O
Spindle motor on/off control output.
4
MDP
O
Spindle motor servo control.
5
MDS
O
:
Toe
'
High, when sampled value of GFS at 460Hz is high.
Low, when sampled value of GFS at 460Hz is low by 8 times successively.
7
NC
8
VCOO
O
Analog EFM PLL oscillation circuit output.
9
VCOI
I
Analog EFM PLL oscillation circuit input. fLOCK=8.6436MHz.
10
TEST
I
TEST pin.
11
PDO
O
Analog EFM PLL charge pump output.
12
VSS
GND.
13
PWMI
I
Spindle motor external control input.
14
V16M
O
VCO? oscillation output for the wide-band EFM PLL.
15
VCTL
I
VCO2 control voltage input for the wide-band EFM PLL.
16
VPCO
O
Wide-band EFM PLL charge pump output.
17
VCKI
I
VCO? oscillation input for the wide-band EFM PLL.
18
FILO
O
Multiplier PLL (slave=digital PLL) filter output.
19
FILI
I
Multiplier PLL filter input.
20
PCO
O
Multiplier PLL charge pump output.
21
AVSS
Analog GND.
22
CLTV
I
Multiplier VCO1 control voltage input.
23
AVDD
Analog power supply (5V).
24
RF
I
EFM signal input.
25
BIAS
I
Constant current input of the asymmetry circuit.
26
ASYI
I
Asymmetry comparator voltage input.
27
ASYO
O
EFM full-swing output.
28
ASYE
I
Low: asymmetry circuit off; high: asymmetry circuit on.
29
NC
30
PSSL
I
Audio data output mode switching input. Low: serial output; high: parallel output.
31
WDCK
O
D/A interface for 48-bit slot. Word clock f=2Fs.
32
LRCK
O
D/A interface for 48-bit slot. LR clock f=Fs.
33
VDD
Power supply (5V).
34
ret
6
DA16 (MSB) output when PSSL=1.
48-bit slot serial data (two's complement, MSB first) when PSSL=0.
35
DAI5
O
DA15 output when PSSL=1.
48-bit slot bit clock when PSSL=0.
e
er
é
DA14 output when PSSL=1.
64-bit slot serial data (two's complement, LSB first) when PSSL=0.
37
DA13
O
DA13 output when PSSL=1.
64-bit slot bit clock when PSSL=0.
38
DA12
O
DA12 output when PSSL=1.
64-bit slot LR clock when PSSL=0.
22

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