Bit clock input terminal.
Duty cycle = 50%, f = 1.4112 MHz
is]
(2) A
VccD
Not connected.
2 QO
|
r Ps) i?) A
Divided clock signal output.
Ground terminal.
XO
XP
XN
'lol
oO
Q Z oO
—_
=
Le
al
—_
wo
VCCE
14,15
=
AA
= ~
ps]
ey
OSR
20
= = o foe}
22
IADJ
N
+}
i)
NS
NS
co
eo
~~
wD
E
10
