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f>VM-20M7MDE
3-5.
B Board
The B board has the digital double scan circuit which convert
1.5K
to EE signal. By this circuit, the PAL field frequency is
made to be lOOHz so that one field signal is made to scan the
CRT two times thus removing the field flicker,
15.K.
input signal to
B
hoard
1H
•• 641,lsec
IV······
20msec
EE Output .Signafl'roin B boird
1H ··•···
32µsec
lV······
IOmsec
(VIDEO)
{V,
SYNC)
-l'Lr
JLJL
j
64µso,
j
I
20msoc
I
The output signal (EE) from the B board is compressed
to
tn
in
time base. JC701, IC702, IC703 constitute an
ND
converter for
TG!Y, B/B-Y, R/R-Y
with the
sampling clock of about 14.2MHz.
IC708, IC709, IC7IO
are
the field memory. IC 711 is the D/A
converterwiththereadclockofabout28.4MHz.
IC? 12
is
the flicker free control CPU having the functions of the
double scan processing ofH. sync, V. sync, frequency division of
28.4MHz clock,
AID
conversion, memory and D/ A timing
control. IC716 selects the sync signal when no signal is input.
IC714 selects the AFC filter. and IC704 is the VCO (with output
ofabout28.5MHz). The output
signal
from the B board
is
supplied
through the low-pass filter of FL708, FL709 and FL710.
In
summary, the B board receives 11K from the A board page 1,
perfonnsthedoublescan(tlickerfree)processingforthesignal
and HIV sync, and outputs them to the A board page 2.
-20-
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