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MDS
(ROUGH/ SPEED)
O SPINOLE
OUT
MDP
(PHASE)
1
a Fs
Spindle signal flow chart
(IC601)
Fig. 41
(2) PLL stage
The present system employs a digital PLL circuit illus-
trated below. This PLL circuit operates so as to lock the
rising edge of a PLCK and the edge of an EFM signal.
Andit has a resolution of as high as approximately eight
times IT (T = EFM signal's bit rate = 1/4.3218 MHz). Both
frequency divider output frequency and EFM bit rate
have their errors automatically regulated to adjust the
mean free-run frequency to the bit rate.
2-multiplier
—_—
F
XTAL V
circuit
bende
(16.934MHz)
Divider
EFMI©
Digital PLL block diagram
(IC701)
Fig. 42
B11
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