THEORY OF CIRCUIT OPERATION
ee eer
ene
i
i
:
|
i
'
! 1.07
P0.0-7 ——
P0.0-7
>
HAVSYNC
vone =
|
RD >) RD
XFR
| CONTROL HBLANK -—— ro
o——>
x1
wR ae WR
>
VBLANK
eo
}
8051
aR
.
<=>
p o .
| P3.0-P3.2
P34
P24-7 |
;
:14 CHANNEL DAS —>
i PWM DAC nasots <>
Y
, Ae
SCL
~¢—peo
HC
pe :
. INTERFACE
o<d—P> HSCL
DDC 1/2 B & FIFO
INTERFACE
i
'
!
i
O~-—B> HSDA
ISDA <+— Po
FUNCTIONAL DESCRIPTIONS
8051 CPU Core
3.
INT1 and T1 input pins are not provided.
Page 24
(Confidential
Do Not Copy,