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4. Block Diagram for High-end models(Back-end)
* FHD 240Hz T480Hz ( 72LM9500)
VLCD_POWER(+12V)
DC-DC Con
DC-DC Con
(TPS54327)
(TPS54327)
Copyright © 2012 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
VLCD_POWER(+12V)
DC-DC Con
+1.5V
DC-DC Con
(TPS54327)
DDR0_A[14:0] /
(TPS54327)
BA[2:0]/CLK/CKE
DDR1_A[13:0]/
DDR3 SDRAM
DDR3 SDRAM
BA[2:0]/CLK/CKE
-
+3.3V
-
1Gbit (x16)
1Gbit (x16)
DDR1_DATA[15:0]
-
800MHz
- 800MHz
I2C_SCL_S
I2C_SDA_S
Vx1
Vx1
Vx1
Vx1
Vx1
Vx1
Rep
Rep
Rep
Rep
Rep
Rep
8Lane Vx1 HS
VLCD_POWER(+12V)
DC-DC Con
DC-DC Con
(TPS54327)
(TPS54327)
VLCD_POWER(+12V)
VCC/VDD/
I2C_SCL_S
PMIC
VGH_A/VGL/
PMIC
(MAX17139)
HVDD/VCORE
I2C_SDA_S
(MAX17139)
DDR3 SDRAM
DDR3 SDRAM
-
-
1Gbit (x16)
1Gbit (x16)
-
800MHz
- 800MHz
DDR0_DATA[15:0]
XTAL_IN
XTAL_OUT
X-Tal
(24.75Mhz)
FRC-III
SPI_DI
SPI FLASH
SPI FLASH
(32Mbit)
(32Mbit)
SPI_DO/CK/CS
(LG1122)
(0x1C, direct
Dual-Link HS-LVDS
0xB2, in-direct)
LG1121_RESET
L/DIM0_VS,
L/DIM0_SCLK/MOSI
8Lane Vx1 HS
Vx1
Vx1
Vx1
Vx1
Vx1
Vx1
Vx1
Vx1
Vx1
Vx1
Rep
Rep
Rep
Rep
Rep
Rep
Rep
Rep
Rep
Rep
8Lane Vx1 HS
VLCD_POWER(+12V)
+1.8V
+2.5V
DC-DC Con
DC-DC Con
(TPS54327)
(TPS54327)
I2C_SCL_S
I2C_SDA_S
* Epoxy 4Layer 1.2T (206x183mm)
L/DIM0_VS
L/DIM0_MOSI/SCLK
I2C_SCL_1
I2C_EN_M
I2C_SDA_1
I2C_SCL_S
I2C HUB
I2C HUB
(PCA9516)
(PCA9516)
I2C_SDA_S
I2C_SCL_2
I2C_EN_S
I2C_SDA_2
VLCD_POWER(+12V)
+0.9V
DC-DC Con
DC-DC Con
(AOZ1038PI)
(AOZ1038PI)
VLCD_POWER(+12V)
+1.8V
DC-DC Con
DC-DC Con
(TPS54327)
(TPS54327)
VLCD_POWER(+12V)
VCC/VDD/
PMIC
VGH_A/VGL/
PMIC
(MAX17139)
HVDD/VCORE
(MAX17139)
LGE Internal Use Only
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