HP 10314D User Manual page 27

Table 2-1. Description of the Status Bits (Continued)
Bit Status Description
Signals
4-7 LBEO-LBE3 Byte Enables vvith BEO the least significant byte and BE3 the
most significant byte. For opcode fetches, the microprocessor
vvill fetch four bytes unless LBS16 is asserted. When LBS16 is
asserted, the microprocessor fetches two bytes.
8 LBS16
If this signal is low for a 16-bit bus cycle, the microprocessor
vvill perform an additional bus cycle if required. For instance,
if LBS16 was low during a memory 'Write vvith all byte enable
(LBE) lines low, the microprocessor would perform a second
bus cycle using the data from the upper two bytes of the data
bus of the first cycle, on the lower two bytes of the data bus for
the second cycle.
9
LNA*
When this signal is low it indicates that the system is requesting
the next address from the microprocessor.
10
LLOCK
When this signal is low it indicates that the microprocessor has
the bus locked to prevent interruption by other bus devices.
11 LERROR* When this signal is low it indicates that the previous
coprocessor instruction generated a coprocessor error.
12
PEREQ*
When this signal is high it requests that the microprocessor
perform a data operand transfer for a coprocessor extension.
13 LBUSY* When this signal is low it indicates the coprocessor is still
executing an instruction.
14 LADS* When this signal is low it indicates a valid bus cycle and address
is available on the microprocessor pins.
15 LREADY* When this signal is low it terminates the bus cycle. This signal
is ignored during bus hold acknowledge.
• This
signal is used for timing analysis purposes when the HP 103140 is operating in the timing mode.
HP 103140
80386DX Preprocessor Interface
Analyzing the Intel 80386DX
2-5