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13.5. Frequency stop detection function
This flag bit indicates the retained status of clock operations or internal data. Its value changes from "0" to "1" when
data loss occurs, such as due to a supply voltage drop. Once this flag bit's value is "1", its value is retained until a
"0" is written to it. This function can not detect voltage down of short time.
During the initial power-on (from 0 V) and if the value of the VLF bit is "1" when the VLF bit is read, be sure to
initialize all registers before using them.
VLF
Write
Read
13.6. FOUT function
The clock signal can be output via the /IRQ1, /IRQ2 pin.
When stopped the /IRQ2 pin output, the pin becomes the Hi-z.
13.6.1. FOUT control register.
Address h
1D
Address h
32
By a combination of FSEL1,FSEL0, an FOUT outputs 32768Hz and 1024Hz and 1Hz and can stop the output.
13.6.2. FOUT function table.
FOUT output pin layout and select the frequency.
FOPIN1
FOPIN0
0
0
At the time of the initial power-on, "0" is set to FSEL1, FSEL0.
Note: The effect of STOP bit to FOUT functions.
When STOP = "1", 32768Hz output is possible.
But 1Hz and 1024Hz output is disabled.
RX8010SJ
ETM37E-07
Data
0
The VLF is cleared to 0, and waiting for next low voltage detection.
1
It is impossible to write in 1 to VLF.
0
RTC register data are valid.
RTC register data are invalid.
1
Should be initialized of all register data.
VLF is maintained till it is cleared by zero.
Function
Extension Register
FSEL1
Function
IRQ Control
Output pin
/IRQ2
0
(CMOS)
/IRQ1
1
(Open-Drain)
Seiko Epson Corporation
Description
bit 7
bit 6
bit 5
FSEL0
USEL
bit 7
bit 6
bit 5
-
-
FSEL1
FSEL0
0
0
0
1
1
0
1
1
0
0
0
1
1
0
1
1
13. How to use
bit 4
bit 3
bit 2
TE
WADA TSEL2 TSEL1 TSEL0
bit 4
bit 3
bit 2
-
TMPIN
output
OFF
1 Hz Output
1024 Hz Output
Don't set it
OFF
1 Hz Output
1024 Hz Output
32768 Hz Output32768 Hz Output
bit 1
bit 0
bit 1
bit 0
FOPIN1 FOPIN0
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INDEX
29
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