Table of Contents
Advertisement
FROM REG
CN16
REG_4.8V
5
6
G
FROM CPU
LCD_CTL
4
F
FROM CPU
DSP_REST
18
E
FROM DSP
HDCVF
15
D
VDCVF
16
FROM CPU
REV_SW
25
HRP1
17
TO DSP
C
FROM DSP
ROUT
GOUT
BOUT
B
0
1
MAIN
A
1
2
T7501
T7501
2
6
CN7601
F7501
F7501
REG_4.8V
3
5
REG_4.8V
4
6
Q7503
Q7503
Q7501
Q7501
10
Q7504
Q7504
Q7502
Q7502
LCD_CTL
1
4
CTL
CTL
OSC
OSC
REG_3.2V
IC7602
R7607
5
L7605
7
6
C7617
R7612
36
34
33
31
30
37
VCO
38
DSP_REST
39
RESET
18
40
COUNTER
MODE SEL
IC7601
PHASE
COMP
QVD
EQ
SEL
PULSE
CANCEL
48
1 2 3 4
5
6
NC
NC
TP7601
HDCVF
15
VDCVF
16
SW
Q7607
RVS_SW
25
HRP1
17
LCD (DAC_3.2V)
3
4
CFL
29
28
27
26
25
STH2
24
STH1
23
22
QH
IC7603
V.SYNC
H.SYNC
21
2
OEH
STV1
20
OEV2
18
FIELD
17
DET
NC
CPV
16
ZOOM
POL
CORRECT
CTL
REG_15V
INT/EXT
15
IC7602
R7604
C7609
POL
14
2
-
-
UD
13
3
R7601,R7602
+
+
LT
R7605
Q7606
7
8
12
SW
NC
NC
CN7601
10
12
14
10
12
14
CN16
Q7011
BUF&SW
Q7013
BUF&SW
Q7015
BUF&SW
5
6
7
LCD MONITOR
0
7
MONITOR
CN7602
L7604
VGH
9
9
REG_15V
L7601
VDD
REG_3.2V
8
8
VEE
MREG_4.8V
11
11
VSS
VSS(REG_-15V)
2
2
CLK1
CLK1
21
21
RL
RL
13
13
CLK2
CLK2
20
20
STV2
STV2
7
7
CLK3
CLK3
19
19
STH2
STH2
12
12
STH1
STH1
24
24
Q2H
Q2H
22
22
4
OEH
OEH
23
23
STV1
STV1
3
3
OEV
OEV
6
6
CPV
CPV
5
5
REG_3.2V
R7645
C7622
VCOM
10
10
R7646
Q7601-Q7604
1
VGL
AMP
1
1
UD
4
4
R
R
15
15
G
G
16
16
B
B
17
17
NV-VZ14EG/EGE/EGM, NV-VZ15B/EG/EGE/EGM/EN, NV-VZ55EG/EGM
8
9
LCD MODULE
MONITOR SYSTEM BLOCK DIAGRAM
10
11
Advertisement
Table of Contents
