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EN 76
9.
LC7.2HU LB
9.2
LCD Power Supply
The Power Supply Unit (PSU) in this chassis is a buy-in and is
a black-box for Service. When defective, a new panel must be
ordered and the defective panel must be returned for repair,
unless the main fuse of the unit is broken. Always replace the
fuse with one of the correct specifications! This part is
commonly available in the regular market.
All Power Supply Units deliver the following voltages to the
chassis:
•
+24 V to the inverters.
•
+12 V to SSB.
•
+12 V and -12 V to Audio Supply.
•
12 V to Bolt-on module.
•
+5 V Standby voltage.
9.3
DC/DC converters
A switch generates the +5.2 V (+5V_SW) from the +5.2 V
(+5V_STANDBY) supply voltage. This switch is mounted on-
board the SSB. This results in the +5V_STANDBY voltage,
coming from the Power Supply Unit, and is used as input for the
on-board DC/DC converters.
They deliver the following voltages to the board:
•
+3.3 V (+3V3_STBY).
•
+5.2 V (+5V_SW).
•
+1.8 V (+1V8S_SW).
•
+3.3 V (+3V3_SW).
An overview can be found in figure "DC-DC converter block
diagram".
Figure 9-4 DC-DC converter block diagram
Circuit Descriptions, Abbreviation List, and IC Data Sheets
9.4
9.5
9.5.1
9.6
(n.a. for LC7.xH)
(n.a. for LC7.xH)
(n.a. for LC7.xH)
G_16860_063.eps
270707
Front-End
Digital inputs are processed by a separate panel that is bolted
on the SSB. This MPEG4 bolt-on module is a "black box" for
Service, and must be swapped when defective. There is no
further information available in this manual.
Video Processing
The video processing is completely handled by the Trident SVP
CX32 video processor which features:
•
CVBS-input for analogue signals.
•
YCbCr-input for digital (DVB/MPEG4) signals.
•
Motion and "edge-adaptive" de-interlacing.
•
Integrated ADC.
•
Built-in 8-bit LVDS transmitter.
•
Color stretch.
•
Skin color enhancement.
•
3D Digital Comb Video Decoder.
•
Interlaced and Progressive Scan refresh.
•
OSD and VBI/Closed Caption.
Video Application
The block diagram "Video" in chapter 6 shows the input and
output signals to and from the Trident Video Processor.
During digital reception, the video signal coming from the
MPEG4 module is fed to the video processor via pins HDMI_Y,
HDMI_Cb, and HDMI_Cr.
The video processor also interfaces the System Interface, i-
Board, CVI and HDMI input.
Memory addressing
Figure "Memory block diagram" shows the interconnection
between the microprocessor, the FLASH memory, the Trident
Video Processor and the SDRAM.
7311
CPU_RST/WR/RD/CE
Reneas
A[0:19]
micro-
processor
D[0:7]
CS/WR/RD
7202
A[0:7]
D[0:7]
CX_BA0/BA1/MCLK/
CLKE/CS0/RAS/CAS/WE
CX_MA[0:11]
DQ[0:15]
Trident CX
CX_BA0/BA1/MCLK/
CLKE/CS0/RAS/CAS/WE
CX_MA[0:11]
DQ[16:31]
Figure 9-5 Memory block diagram
Control signals CPU_RST, WR, RD and CE, address lines
A[0:19] and data lines D[0:7] are used for transferring data
between the microprocessor (item 7311) and the flash memory
(item 7310). Control signals CS, WR and RD, address lines
A[0:7] and data lines D[0:7] are used for transferring data
between the Trident Video Processor (item 7202) and the
microprocessor (item 7311). Control signals CX_BA0,
CX_BA1, CX_MCLK, CX_CLKE, CX_CS0, CX_RAS, CX_CAS
and CX_WE, address lines CX_MA[0:11] and data lines
DQ[0:15] are used for transferring data between the Trident
Video Processor and the SDRAM ICs (items 7204 and 7205).
7310
1MB
Flash Memory
7204
8MB
SDRAM
7205
8MB
SDRAM
G_16860_062
220207
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