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• Up to 2.38 Gbps throughput
• Up to 297.5 Megabytes/sec bandwidth
• 345 mV (typ) swing LVDS devices for low EMI
• PLL requires no external components
• Compatible with TIA/EIA-644 LVDS standard
• Low profile 56-lead or 48-lead TSSOP package
• DS90C385 also available in a 64 ball, 0.8mm fine pitch ball grid array (FBGA) package
11.21.3. Pin Descriptions
DS90C385 MTD56 (TSSOP) Package Pin Description — FPD Link Transmitter
Pin name
I/O
TxIN
I
TxOUT+
O
TxOUT-
O
TxCLKIN
I
R_FB
I
TxCLK OUT+
O
TxCLK OUT-
O
PWR DOWN
I
V
I
CC
GND
I
PLL V
I
CC
PLL GND
I
LVDS V
I
CC
LVDS GND
I
DS90C385SLC SLC64A (FBGA) Package Pin Summary — FPD Link Transmitter
Pin name
I/O
TxIN
I
TxOUT+
O
TxOUT-
O
TxCLKIN
I
R_FB
I
TxCLK OUT+
O
TxCLK OUT-
O
PWR DOWN
I
V
I
CC
GND
I
PLL V
I
CC
PLL GND
I
LVDS V
I
CC
LVDS GND
I
NC
DS90C385SLC SLC64A (FBGA) Package Pin Description — FPD Link Transmitter
Pin
Pin Name
A1
TxIN27
A2
TxOUT0-
A3
TxOUT0+
A4
LVDS VCC
A5
LVDS VCC
A6
TxCLKOUT-
A7
TxCLKOUT+
A8
TxOUT3+
B1
TxIN1
22" TFT TV Service Manual
No.
Description
28
TTL level input. This includes: 8 Red, 8 Green, 8 Blue, and 4 control lines -FPLINE,
FPFRAME and DRDY (also referred to as HSYNC, VSYNC, Data Enable).
4
Positive LVDS differentiaI data output.
4
Negative LVDS differential data output.
1
TTL Ievel clock input. Pin name TxCLK IN.
1
Programmable strobe select
1
Positive LVDS differential clock output.
1
Negative LVDS differential clock output.
1
TTL level input. Assertion (low input) TRI-STATES the outputs, ensuring low
current at power down.
3
Power supply pins for TTL inputs.
4
Ground pins for TTL inputs.
1
Power supply pin for PLL.
2
Ground pins for PLL.
1
Power supply pin for LVDS outputs.
3
Ground pins for LVDS outputs.
No.
Description
28
TTL level input.
4
Positive LVDS differentiaI data output.
4
Negative LVDS differential data output.
1
TTL Ievel clock input. The rising edge acts as data strobe. Pin name TxCLK IN.
1
Programmable strobe select. HIGH = rising edge, LOW = falling edge.
1
Positive LVDS differential clock output.
1
Negative LVDS differential clock output.
1
TTL level input. Assertion (low input) TRI-STATES the outputs, ensuring low
current at power down.
3
Power supply pins for TTL inputs.
4
Ground pins for TTL inputs.
1
Power supply pin for PLL.
2
Ground pins for PLL.
1
Power supply pin for LVDS outputs.
3
Ground pins for LVDS outputs.
6
Pins not connected.
Type
I
O
O
P
P
O
O
O
I
Pin
D3
E4
E8
G1
G6
B3
B4
B7
D5
28
Pin Name
Type
GND
G
GND
G
GND
G
GND
G
GND
G
LVDS GND
G
LVDS GND
G
LVDS GND
G
LVDS GND
G
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