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AIN SIGNAL PATH PLAYBACK MODE
LB3305
VLP0157
C3310
6V47
LB3304
LB3306
VLP0157
VLP0157
C3323
LB3308
6V47
VLP0157
C3327
0.01
LB3303
VLP0157
C3326
0.01
C3321
6V47
80
R3305
C3325
22K
1
1.1
YC IN
81
PED.
82
VSS YAD
C3324
CLAMP
1
1.1
Y IN
83
2.5
84
VDD YAD
C3318 0.01
0.8
C3322
85
VRB YAD
0.1
C3317 0.01
0.8
86
VRB CAD
2.5
87
VDD CAD
1.2
C IN
88
C3320
89
VSS CAD
0.1
C3315 0.01
BIAS
1.7
90
VRT CAD
C3319
91
A VSS1
0.1
2.5
92
VDD YCDA
1.7
C OUT
D/A
93
8FSC
94
VSS YCDA
1.5
Y OUT
D/A
95
8FSC
C3314 0.01
1.2
96
BIAS DA2
C3313 0.01
0.8
97
BIAS DA1
C3312 0.01
0.9
98
VREF DA
99
A VSS2
2.5
100
VDD PLL
IC3301
40
TC90A88F
(3D Y/C SEP.&
3D NR TBC)
C3311
C3309
0.1
0.1
1.5
BRACKETS ON THIS DIAGRAM IS PLAYBACK MODE
6
45
A2
A1
LB3309
LB3310
VLP0157
VLP0157
C3332
6V47
R3306
0
79
78
77
76
75
74
73
72
71
REC
A/D
4FSC
PB
A/D
4FSC
UP
SAMPLING
+
UP
SAMPLING
1
2
3
4
5
6
7
8
9
10
L3313
C3308
R3303
33u
1500P
0
C3371
R3318
39P
4700
B3
B8
7
8
IC3303
PQ1K253M2ZP
(2.5V REG.)
LB3307
VLP0157
3.4
2.5
1
VIN
VOUT
6
C3350
16V10
2
GND
GND
5
3.4
1.3
3
VC
NR
4
C3351
0.01
C3353
6V47
C3331
C3328
0.1
0.1
70
69
68
67
66
65
64
63
62
61
3D
MEMORY
Y/C
SEP.
DECODER
ENCODER
EQ
CNR
(BURST CHANGE)
BLACK
DELAY
EQ
EXPANSION
YNR
ADJ.
YNC
(SYNC
LNR
CHANGE)
11
12
13
14
15
16
17
18
19
20
C3307
C3306
0.1
0.1
9
IC3302
R3112N251A
(RESET)
3.4
1
OUT
R3307
10K
3.4
2
VDD
3
GND
C3329
0.1
60
59
58
57
56
55
54
53
52
51
DELAY
ADJ.
SYNC
TBC
TIMING
CONTROL
3D
DNR
REC
PB
REC
PB
21
22
23
24
25
26
27
28
29
30
C3305
0.1
B9
NV-HS880EG/B/EC/EE
TBC/DNR PACK SCHEMATIC DIAGRAM
10
A4
A5
A3
2.1
CD
5
C3330
R3301
8200P
15K
4
R3302
33K
C3303
0.1
2.5
VDD RAM2
50
TBC WE
3.3
49
LB3311
VLP0157
HSW IN
2.4
48
PV IN
47
LB3301
VLP0157
ADV OUT
0.1
46
D VSS2
45
0
OSD CK
44
2.5
D VDD2
43
TEST 3
42
C3302
0.1
TEST 2
41
TEST 1
40
VSS IO2
39
0
HD OUT
38
0
VD OUT
37
3.4
VDD IO2
36
OSD A2
35
C3301
0.1
OSD A1
34
OSD B
33
OSD G
32
OSD R
31
R3308
10K
B1
11
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