Cpu And Peripheral Circuit - Alinco DR-M03R Service Manual

3. Phase Comparator Circuit
4. PLL Loop Filter Circuit
5. VCO Circuit
4) CPU and Peripheral Circuits
1. LCD Display Circuit
2. Reset and Backup
3. S (Signal) Meter Circuit
4. DTMF Encoder
5. Tone Encoder
6. DCS Encoder
The PLL (IC116) uses the reference frequency, 5 or 6.25 kHz. The phase
comparator in the 10116 compares the phase of the frequency from the
VCO with that of the comparison frequency, 5 or 6.25 kHz, which is
obtained by the internal divider in IC116.
If a phase difference is found in the phase comparison between the
reference frequency and the VCO output frequency, the charge pump
output (pin 5) of IC116 generates a pulse signal, which is converted DC
voltage by the PLL loop filter and input to the input to the variable
capacitor of the VCO unit for oscillation frequency control.
AColpitts oscillation circuit driven by Q131 directly oscillates the desired
frequency. The frequency control voltage determine in the CPU (IC1) and
PLL circuit is input to the variable capacitor (D123). This change the
' oscillation frequency, which is amplified by the VCO buffer (Q134, Q145)
and output from the VCO area.
The CPU turns ON the LCD via segment and common terminals with 1/4
the duty and 1/3 the bias, at the frame frequency is 64 Hz.
When the power from the DC cable increases from Circuits 0 V to 2.5 V or
more, "H" level reset signal is output from the reset IC (IC4) to pin 33 of
the CPU (1C1), causing the CPU to reset. The reset signal , however,
waits at 100, and dose not enter the CPU until the CPU clock (X1) has
stabilized.
The DC potential of IF IC is input to pin 1 of the CPU (IC1), converted from
an analog to a digital signal, and displayed as the S-meter signal on the
LCD.
The, CPU (IC1) is equipped with an internal DTMF encoder. The DTMF
signal is* output from pin 10, through R35, R34 and VR109 (for level
adjustment), and then through the microphone amplifier (1C114:D), and is
sent to the variable capacitor of the VCO for modulation. At the same time,
the monitoring tone passes through the AF circuit and is output from the
speaker.
The CPU (IC1 ) is equipped with an internal tone encoder. The tone signal
(67.0 to 250.3 Hz) is output from pin 9 of CPU to the variable capacitor
(D123) of the VCO for modulation.
The CPU (1C1 ) is equipped with an internal DCS code encoder. The code
(023 to 754) is output from pin 9 of CPU to the variable capacitor (D601) of
the PLL reference oscillator. When DCS is ON, DCS MUTE circuit
(Q126-ON, Q133-ON, Q 132-OFF) works. The modulation activates in
X601 side only.
c
5