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3.1.4
Port0:003h / Port1:203h CPU_IntStat (CPU Interrupt Status)
Base Address: Port0=000h, Port1=200h
Mode
Ofst Adrs
Register Name
Device
003h
CPU_IntStat
/ Host
Indicates CPU interface-related interrupts.
All bits can be set to "1" to clear the interrupt factors.
Bit7
RAM_RdCmp
Directly specifies interrupt factors.
Set to "1" when data is read from the RAM by the RAM_Rd function and the RAM_Rd_XX data is
enabled.
Bit6-2
Reserved
Bit1
DMA_CountUp
Directly specifies interrupt factors.
Set to "1" when the DMA_Count_HH,HL,LH,LL values overflow while the transfer mode operates
in free-run mode. The DMA_Count_HH,HL,LH,LL values return to 0, and DMA operation
continues.
Bit0
DMA_Cmp
Directly specifies interrupt factors.
Set to "1" when the DMA transfer is stopped or if the specified transfer quantity has been sent and
end processing is complete.
S2R72V18 Technical Manual (Rev.1.00)
R/W
Bit Symbol
R (W)
7: RAM_RdCmp
6:
5:
4:
3:
2:
R (W)
1: DMA_CountUp
R (W)
0: DMA_Cmp
EPSON
Description
0: None
1: RAM Read Complete
0:
1:
0:
1:
0:
1:
0:
1:
0:
1:
0: None
1: DMA Counter Overflow
0: None
1: DMA Complete
3. Register Details
Reset
00h
213
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