1. Manuals
  2. Brands
  3. Intel Manuals
  4. Receiver
  5. STEL-2176
  6. User manual

Intel STEL-2176 User Manual

Digital mod/demod asic 16/64/256 qam receiver with fec qpsk/16 qam transmitter with fec
Hide thumbs
Table of Contents

Advertisement

Quick Links

Download this manual
查询STEL-2176供应商
STEL-2176
User Manual
STel-MAN-97709
R

Advertisement

Table of Contents
loading

Summary of Contents for Intel STEL-2176

  • Page 1 查询STEL-2176供应商 STEL-2176 User Manual STel-MAN-97709...
  • Page 2 TRADEMARKS ® ® Stanford Telecom and STEL are registered trademarks of Stanford Telecommunications, Incorporated. STEL-2176 User Manual...
  • Page 3 Recipients of this User Manual should note that the content contained here-in is subject to change. The content of this User Manual will be updated to reflect the latest technical data, without notice to the recipients of this document. User Manual STEL-2176...
  • Page 4 ERRATA for STEL-2176 Supported Modes of Operation: Downstream 16 QAM 64 QAM 256 QAM Annex A Annex B Annex C Upstream BPSK QPSK 16 QAM MCNS DAVIC STEL-2176 User Manual...

  • Page 5: Table Of Contents

    GAPS, SERIAL MODE ......................... TRANSMITTER............................. INTRODUCTION ..........................FUNCTIONAL BLOCK DIAGRAM DESCRIPTIONS ................DATA PATH DESCRIPTION ....................... Bit SYNC Block ..........................Bit Encoder Block ........................... Symbol Mapper Block........................Nyquist FIR Filter........................... Interpolating Filter ......................... Modulator ............................. 10-Bit DAC............................. User Manual STEL-2176...
  • Page 6 Master Transmit Clock Generator ....................Clock Generator ..........................NCO.............................. TRANSMIT REGISTER DESCRIPTIONS....................Programming the 2176 Transmit and Receive Functions..............Block 2, Upstream Registers (Group 4) ..................... TIMING DIAGRAMS ..........................BURST TIMING EXAMPLES ......................... RECOMMENDED INTERFACE CIRCUITS .................... STEL-2176 User Manual...
  • Page 7 LIST OF FIGURES FIGURE PAGE Reference A/D Wiring....................Example Output Load Schematic................STEL-2176 Receiver Block Diagram ................Master Receive Clock Generator................. QAM Demodulator Blocks..................ITU-T (J.83) Annex A FEC Subsystem ................. 16 QAM Constellation ....................64 QAM Constellation ....................256 QAM Constellation (DAVIC)................
  • Page 8 LIST OF TABLES TABLE PAGE STEL-2176 Pin Assignments ..................Absolute Maximum Ratings ..................Recommended Operating Conditions ................. ADC Performance Specifications ................DC Characteristics ..................... Read/Write Register Set..................... Write Only Registers: ....................Group 2, Sub-Group 'A' Read/Write Registers............. Sub-Group 'A' Read-Only Registers ................
  • Page 9 Interpolation Filter Bypass Control ................Interpolation Filter Signal Level Control ..............Signal Inversion Control .................... FCW Selection......................Addresses of the STEL-2176 Register Groups .............. Transmit Block 2 Register Data Fields ................. Clock Timing AC Characteristics................Pulse Width AC Characteristics.................. Bit Clock Synchronization AC Characteristics..............

  • Page 10: Key Features

    Standards Carrier frequencies programmable from 5 Supports low data rates for voice to 65 MHz applications and high data rates for Uses inexpensive crystal in 25 MHz range wideband applications Operates in continuous and burst modes STEL-2176 User Manual...

  • Page 11: Introduction

    INTRODUCTION The STEL-2176 is a complete subscriber-side cable Interleaver puts the data bits back into the original modem chip that integrates both receiver and order, while Trellis and Reed-Solomon decoders handle transmitter functions. It is offered in CMOS .35 micron error correction.

  • Page 12: Mechanical Specifications

    Introduction MECHANICAL SPECIFICATIONS 208-PIN SQFP PACKAGE Dimensions are in mil l imeters. TPG 53310. c-7/ 2 9/97 Table 1. STEL-2176 Pin Assignments Pin No. Pin Name Pin Type Pin Description Ground Power Dedicated to crystal oscillator at pins 3 & 4...
  • Page 13 Control/Status register parallel data in/out Ground RXRESCLK Output FEC test clock output (8 times RX symbol rate) Power RXTSTDOUT[9] Output Test mux output RXTSTDOUT[8] Output Test mux output RXTSTDOUT[7] Output Test mux output RXTSTDOUT[6] Output Test mux output STEL-2176 User Manual...
  • Page 14 Input buffer bias. Set to 3.3V or 5V dep. on max. input V. voltage. RXRSTB Input Receiver reset (active low) Ground RXPDATAOUT[7] Output Receive parallel output data RXPDATAOUT[6] Output Receive parallel output data RXPDATAOUT[5] Output Receive parallel output data User Manual STEL-2176...
  • Page 15 Ground (analog) Dedicated to analog section of ADC (See Figure 1) VDDA Power (analog) Dedicated to analog section of ADC (See Figure 1) VCMA Analog output From ADC (See Figure 1) Power Dedicated to digital section of ADC STEL-2176 User Manual...
  • Page 16 Analog GND (VSSA) µF µF µF µF µF µF µF µF µF Digital Supply (VDD) STEL-2176 Figure 1. Reference A/D Wiring T1-6TKK81 0.1 µF 0.1 µF Note 1 50 line DACOUTP load 0.1 µF DACOUTN Mini- Circuits Note 1: Normally some application dependent alias filtering and amplitude control appear at this point in the circuit WCP 53807.c-12/5/97...

  • Page 17: Electrical Specifications

    The STEL-2176 electrical characteristics are provided by Table 2 through Table 4. WARNING Stresses greater than those shown in Table 2 may cause permanent damage to the STEL-2176. Exposure to these conditions for extended periods may also affect the STEL-2176 reliability.
  • Page 18 Output Capacitance All outputs Output Full Scale DAC Current Single output DAC Compliance Voltage Volts Based on 50 ohms load ±0.96 (Differential) resistance to ground. DAC Output Resistance DAC Output Capacitance NOTES: Current source to ground output. User Manual STEL-2176...

  • Page 19: Receiver

    OVERVIEW two output signals to adjust the RF and IF analog gain stages of circuitry external to the STEL-2176, so that the The STEL-2176 is a complete subscriber-side cable ADC input is in the optimal range. The two outputs can...

  • Page 20: Functional Blocks

    Receiver Description correctable by the FEC. The STEL-2176 internal memory by-passed for ATM applications. The output can be 8- can support all MCNS Interleaver configurations. For bit parallel with a byte clock or serial with a bit clock. deeper interleaving, a direct interface to external The data can be output in a smooth fashion without memory is provided.

  • Page 21: Master Receive Clock Generator

    The Oscillator signal (RXOSCIN and Master Receive Clock Generator RXOSCOUT) is four times the signal symbol rate. The STEL-2176 uses a master clock (MCLK) to control • The value of M and N should be selected so the receive timing functions. MCLK can be generated in MCLK is four times the value of the Oscillator either of three ways as shown in Figure 4.

  • Page 22: Qam Demodulator Blocks

    These higher frequency terms are removed by an image filter. OutA OutB Automatic Frequency control (AFC) The STEL-2176 can accommodate up to ±200 kHz (1 sample/ Timing uncertainty in the carrier frequency. The carrier (to FEC) symbol)

  • Page 23: Fec Decoder Blocks

    FEC blocks in the receiver is in setting AGC_ThresholdA (Bank 0 Register 14 ) and reverse order from the transmitter. The STEL-2176 FEC AGC_ThresholdB (Bank 0 Register 15 ) to slightly subsystem can decode signals which are generated in different values.
  • Page 24 The remaining bits Byte Conversion . . . b are fed directly to the frame sync. Differential Decoder Differential Decoder WCP 53708.c-10/28/97 Two bits (I ) of each symbol are differentially Figure 11. Demapper decoded according to the equation: User Manual STEL-2176...

  • Page 25: De-I Nterleaver

    MISS (Block 1 Register The function of the output clock block is to evenly ) times. distribute the output receive data of the STEL-2176 and to eliminate gaps caused by the FEC subsystem. The De-I nterleaver output of the Reed-Solomon decoder is 188 bytes of data for every 204 input bytes.
  • Page 26 010,011 011,001 000,011 001,001 000,001 001,101 100,001 101,101 010,110 011,100 000,110 001,100 000,010 001,110 100,010 101,110 110,011 111,001 100,011 101,001 010,001 011,101 110,001 111,101 110,110 111,100 100,110 101,100 010,010 011,110 110,010 111,110 WCP 53709.c-10/29/97 Figure 15. 64 QAM Mapping User Manual STEL-2176...
  • Page 27 Differential Decoder Register 55 ) times, the frame sync block declares The two bit streams coming out of the Viterbi decoder ÒacquisitionÓ and starts further processing of the data. are fed into the differential decoder. The differential STEL-2176 User Manual...

  • Page 28: Derandomizer

    ÒtrueÓ for this block. This flag The Derandomizer uses a linear feedback shift register propagates to the STEL-2176 RXDECDFLG output. as shown below. It works in GF (128). The delay elements are initialized at the beginning of each frame...

  • Page 29: Receive And Universal Register Descriptions

    The registers can be FUNCTIONS accessed using the Microcontroller Interface's parallel The STEL-2176 has a combination of universal, receive or serial interface (see page 11). and transmit registers. The registers are arranged as three banks of registers (Bank 0, Bank 1, and Bank 2).
  • Page 30 Once the search is externally initiated the value should be returned to VitFeedBackEn Setting the value to 1 enables the use of Viterbi Decoder feedback for using the VitFeedBack register to force the Frame Sync circuit to search for the start of the symbol group. User Manual STEL-2176...

  • Page 31: Bank 0 - Qam Demodulator Registers Universal Registers (Group 2)

    = 64 QAM, or 54 = 256 QAM Factory Defined Value - 5F = 16 QAM, 76 = 64 QAM, or A4 = 256 QAM Table 9. Sub-Group 'A' Read-Only Registers Address SymbolCnt[1:0] AcquisitionLock AcquisitionFail State SymbolCnt[9:2] SymbolKCnt AcquireCnt ErrPwr JitPwr STEL-2176 User Manual...
  • Page 32 Receiver Description Bank 0, Group 2, Sub-Group 'A' Register Data Field Descriptions AcquireCnt The value indicates the number of times the STEL-2176 has attempted to acquire the signal. AcquisitionFail The value is set to 1 when an acquisition failure is declared due to excessive error power;...
  • Page 33 Address Factory Use Only Factory Use Only DDC_DeltaTheta[3:0] DDC_DeltaTheta[11:4] Factory Use Only DDC_DeltaTheta [13:12] Factory Use Only Factory Use Only Factory Use Only Factory Use Only AGC_PowerEstimate[7:0] Factory Use Only AGC_PowerEstimate[9:8] Factory Use Only Factory Use Only STEL-2176 User Manual...
  • Page 34 Factory Use Only This data field is used by the factory and its function is not related to the STEL-2176 receive and transmit characteristics. Nyquist_AlphaSel[1:0] Selects the excess BW of the Nyquist matched filter: 00 ->...
  • Page 35 Factory Use Only This data field is used by the factory and its function is not related to the STEL-2176 receive and transmit characteristics. Pwrlvl_powerEstimate[10:0]...
  • Page 36 WQ2[15:8] WI3[7:0] WI3[15:8] WQ3[7:0] WQ3[15:8] WI4[7:0] WI4[15:8] WQ4[7:0] WQ4[15:8] WI5[7:0] WI5[15:8] WQ5[7:0] WQ5[15:8] WI6[7:0] WI6[15:8] WQ6[7:0] WQ6[15:8] WI7[7:0] WI7[15:8] WQ7[7:0] WQ7[15:8] WI8[7:0] WI8[15:8] WQ8[7:0] WQ8[15:8] WI9[7:0] WI9[15:8] WQ9[7:0] WQ9[15:8] WI10[7:0] WI10[15:8] WQ10[7:0] WQ10[15:8] WI11[7:0] WI11[15:8] WQ11[7:0] WQ11[15:8] User Manual STEL-2176...
  • Page 37 Update_En Factory Defined Value - ShiftSel_W_DD[1:0] Factory Defined Value - 7F Table 18. Group 2, Sub-Group 'E' Read-Only Registers Address WI0[7:0] WQ0[3:0] WI0[11:8] WQ0[[11:4] WI1[7:0] WQ1[3:0] WI1[11:8] WQ1[[11:4] WI2[7:0] WQ2[3:0] WI2[11:8] WQ2[[11:4] WI3[7:0] WQ3[3:0] WI3[11:8] WQ3[[11:4] WI4[7:0] STEL-2176 User Manual...
  • Page 38 Factory Defined Value - 1F Factory Defined Value - 7 Factory Defined Value - 88 Factory Defined Value - 14 Factory Defined Value - 88 Factory Defined Value - 14 Factory Defined Value - 88 Factory Defined Value - 14 User Manual STEL-2176...

  • Page 39: Bank 1 - Fec Registers (Group 3)

    Reed-Solomon Decoder , and 74 to 73 Bank 1, Group 3, Sub-Group 'A' - Viterbi and De-Mapper Registers Table 21. Group 3, Sub-Group 'A' Read/Write Registers Address DVB & IEEE Factory Defined Value - 3 802.14 map STEL-2176 User Manual...
  • Page 40 Bank 1, Group 3, Sub-Group 'C' - De-I nterleaver Registers Table 23. Group 3, Sub-Group 'C' Read/Write Registers Address Not used ShadowMode Level2 Not used TestMode I_test Not used J_test Table 24. Group 3, Sub-Group 'C' Read-Only Registers Address I_test J_test SRAM_addr[15:8] SRAM_addr[7:0] User Manual STEL-2176...
  • Page 41 Bank 1, Group 3, Sub-Group 'D' - MPEG FrameSync Registers Table 25. Group 3, Sub-Group 'D' Read/Write Registers Address MISS SyncSymbol Not used OP_ERR Table 26. Group 3, Sub-Group 'D' Read-Only Registers Address Factory Use Only Factory Use Only Factory Use Only Factory Use Only STEL-2176 User Manual...
  • Page 42 The number of Syncs that must be detected before data is output. MISS The number of misses before the Frame Sync state machine goes into idle. SyncSymbol Used in Annex A only to input an arbitrary FRAME sync symbol; normally 47 User Manual STEL-2176...
  • Page 43 Table 30. Group 3, Sub-Group 'G' Read/Write Registers Address Factory Defined Value - CC = Annex A:, 80 = Annex B: Not Used OutputDataRate Not Used CLR_ERR Table 31. Group 3, Sub-Group 'G' Read-Only Registers Address Error_cnt[7:0] Error_cnt[15:8] STEL-2176 User Manual...

  • Page 44: Timing

    8Ênanoseconds. gaps in the transmission of the MPEG-2 frame. But the STEL-2176 provides the option of spreading the The Output Clock goes for 188 bytes, then the data gap over a frame so there appears to be no gap. For and clock stop until Frame-Sync/ is asserted again.

  • Page 45: Downstream Output Timing (Serial Output)

    Output Clock ~50% Byte’s Period TPG 53298.c-7/28/97 Figure 19. DOWNSTREAM OUTPUT TIMING (SERIAL OUTPUT) Case 1: No Gaps between MPEG-2 Frames. Frame-Sync/ D ata, MSB, or LSB first Output Clock ~50% bits’s Period TPG 53300.c-7/28/97 Figure 20. STEL-2176 User Manual...

  • Page 46: Downstream Output Timing (Parallel Data Output)

    Frame -Sync/ Data, MSB, or L SB first Output Clock ~8 n.sec After 8*204 clocks and 8*204 bITS, starting fro m the Frame Sync, The output clock will stay ‘low’ till next Ftame Sync. TPG 53297.c-7 /28/97 User Manual STEL-2176...

  • Page 47: De-Interleaver External Sram Timing

    DE-INTERLEAVER EXTERNAL SRAM TIMING Internal clock (RES_CLK) SRAM ADDRESS SRAMOEb_ 15 nsec min. 15 nsec min. 15 nsec min. SRAMWEb_ SRAMDATA 15 nsec max 0 nsec min. 15 nsec min. 15 nsec min. 15 nsec min. WCP 53888.C-12/6/97 Figure 23. STEL-2176 User Manual...

  • Page 48: Transmitter

    RF signal. programmed. The STEL-2176 is the latest in a series of modulator In addition, the STEL-2176 is designed to operate chips that comprise the STEL-1103 through from a 3.3 Vdc power supply and the chip can be...
  • Page 49 V DD MASTER CLOCK (CLK) TXRSTB TXBITCLK TXSYMPLS Master Clock TXACLK TXCLKEN Generator TXCLK COS 2πFT TXNCOLD TXFCWSEL SIN 2πFT Numerically Controlled Oscillator DATA ADDR Interface Unit (Group 2 Registers) WCP 53806.c-12/7/97 Figure 24. STEL-2176 Transmitter Block Diagram STEL-2176 User Manual...

  • Page 50: Bit Encoder Block

    TXTCLK is re-latched internally by the Data Path Control (Multiplexers) next falling edge of TXBITCLK which re-synchronizes The STEL-2176 provides a great deal of flexibility and the data to the internal master clock. control over the routing of data through or around the encoding functions.
  • Page 51 The scrambler may be either frame synchronized might otherwise arise from the occurrence of repeating or self synchronized. Table 35 shows the registers patterns in the input data. The Scrambler (Figure 26) involved. uses Pseudo-Random (PN) generator STEL-2176 User Manual...
  • Page 52 Register 31 Register 30 (INIT Reg) Bit 7 to Bit 0 Bit 7 to Bit 0 Bit 7 to Bit 0 0000Ê0000 0000Ê0000 1010 1001 Scrambler Frame synchronized (sidestream) Register 36 Bit 4 Type Set to zero User Manual STEL-2176...
  • Page 53 RS Encoder inserts its checksum (2T bytes of data) Reed - Solomon Encoder into the data path. There is no adverse effect to letting The STEL-2176 uses a standard Reed-Solomon (RS) TXTCLK or TXTSDATA continue to run during the Encoder for error correction encoding of the serial data checksum;...

  • Page 54: Symbol Mapper Block

    Mapper to determine the output bit values (i.e., I between user input pin control or register control is , and Q ), which are routed to the Symbol Mapper. made in another register bit, as shown in Table 39. User Manual STEL-2176...
  • Page 55 The result is a Table 40. QPSK Differential Encoding and Phase Shift Current Input Current Output Next Output Phase Shift (IQ) (IQ) (IQ) (degrees) -90 (CW) 90 (CCW) -90 (CW) 90 (CCW) 90 (CCW) 90 (CCW) 90 (CCW) -90 (CW) STEL-2176 User Manual...
  • Page 56 Symbol Mapping field (bits 7-5 of Block 2 Register 2E (Figure 31) is the natural constellation for the will map the four input bits to a new value, as indicated STEL-2176. in Table 41. If the MSB of the Symbol Mapping field is set to 1, bits...
  • Page 57 1001 1010 1011 1011 1011 0111 1010 1011 1010 1010 1001 0110 1011 1100 1100 1100 1100 1100 1100 1101 1101 1110 1101 1110 1101 1110 1110 1101 1110 1101 1110 1111 1111 1111 1111 1111 1111 STEL-2176 User Manual...

  • Page 58: Gray Coded Constellation

    Transmitter Description WCP 52988.c-10/29/97 WCP 52990.c-4/26/97 Figure 32. Gray Coded Constellation Figure 34. DAVIC Coded Constellation WCP 52989.c-4/26/97 WCP 52991.c-4/26/97 Figure 33. Left Coded Constellation Figure 35. Right Coded Constellation User Manual STEL-2176...

  • Page 59: Nyquist Fir Filter

    The Interpolating Filter, shown in Figure 37, is a WCP-52992.c-4/26/97 configurable, three-stage, interpolating filter. The filter Figure 36. Nyquist FIR Filter increases the STEL-2176Õs sampling rate (to permit the wide range of RF carrier frequencies possible) by interpolating between the FIR filter steps at the master clock frequency.

  • Page 60: Modulator

    NCO. The I channel signal is multiplied by the cosine output from the NCO and the Q channel signal is multiplied by the sine output. The resulting modulated sine and cosine carriers are applied to an adder and either added or subtracted User Manual STEL-2176...

  • Page 61: 10-Bit Dac

    ) is used to select one Master Transmit Clock Generator of the 90 Block 2 Registers by placing its address on the The STEL-2176 uses a master clock (CLK) to control the ADDR bus lines. The data bus (DATA ) is an 8-bit, transmit timing functions.

  • Page 62: Clock Generator

    ≤ ≤ N 1 3 N 4095 The timing of the STEL-2176 is controlled by the Clock Generator, which uses an master clock (CLK) and The symbol pulse (TXSYMPLS) signal output is programmable dividers to generate all of the internal intended to allow the user to verify synchronization of and output clocks.

  • Page 63: Transmit Register Descriptions

    Receiver Section (see page 20). The registers comprising Bank 2 are described The STEL-2176 has a total of xxx registers and they are below. When the Bank 2 (Group 4) registers are arranged as three banks of registers. As indicated in...
  • Page 64 Sixteen 10-bit FIR coefficients. Each coefficient is applied to two taps of the FIR filter to Coefficients control its filter characteristics. FZSINB Controls the sine component of the NCO output. Setting the field to 0 rotates the constellation by 45° for on-axis modulation of a BPSK signal. User Manual STEL-2176...
  • Page 65 Sets the error correction capability of the error correction encoding. TCLK Sel. Selects an externally generated clock for external control of data latching. TRLSBF Determines whether the first input bit is the MSB or LSB of the byte applied to the RS Encoder. STEL-2176 User Manual...

  • Page 66: Timing Diagrams

    = 0 V, T = Ð40° to 85° C) Symbol Parameter Min. Nom. Max. Units Conditions Clock Frequency ( Clock Period nsec Clock High Period nsec CLKH Clock Low Period nsec CLKL Clock Rising Time nsec Clock Falling Time nsec User Manual STEL-2176...
  • Page 67 = 3.3 V ±10%, V = 0 V, T = Ð40° to 85° C) Symbol Parameter Min. Nom. Max. Units Conditions Clock Enable (TXCLKEN) Low nsec Reset (TXRSTB) Low nsec RSTL NCO Load (TXNCOLD) High CLK cycles NLDH STEL-2176 User Manual...
  • Page 68 = 3.3 V ±10%, V = 0 V, T = Ð40° to 85° C) Symbol Parameter Min. Nom. Max. Units Conditions Clock to TXBITCLK, TXSYMPLS, TXDATAENO, or nsec TXACLK edge Clock Enable (TXCLKEN to TXTCLK Setup) nsec CESU User Manual STEL-2176...
  • Page 69 (TXDATAENI, TXDIFFEN, TXRDSLEN, TXSCRMEN) at the falling edges of TXBITCLK. Note 3: In the STEL-2176, data is latched on the rising edge of the CLK that follows the falling edge of TXBITCLK. Thus, the data validity window is one CLK period (t ) delayed.
  • Page 70 CSSU Chip Select ( CS ) Hold nsec CSHD Write Setup ( WRB ) nsec WRSU Write Hold ( WRB ) nsec WRHD Data Strobe Pulse Width nsec DSBL Data Hold Time nsec Data Setup Time nsec User Manual STEL-2176...
  • Page 71 Nom. Max. Units Conditions Address Valid Period nsec Address to Data Valid Delay nsec Address to Data Invalid Delay nsec ADIV Data Valid After Chip Select Low nsec DVCSL Data Invalid After Chip Select High nsec DICSH STEL-2176 User Manual...
  • Page 72 CLK cycles FCWHD TXDATAENO Low to Zero Frequency Out Delay CLK cycles DENLZ TXDATAENO High to Valid Frequency Out CLK cycles DENHV Delay TXDATAENO to TXFCWSEL Valid CLK cycles DOFCWV TXDATAENO to TXFCWSEL Invalid CLK cycles DOFCWI User Manual STEL-2176...
  • Page 73 Auxiliary Clock (TXACLK) Low (n-1) CLK cycles Note 1 ACKL Symbol Pulse (TXSYMPLS) High CLK cycles TXBITCLK Low to TXDATAENO edge CLK cycles DENOD Notes: ÒnÓ is the 4-bit binary value in Block 2 Register 2A bits 3-0. STEL-2176 User Manual...

  • Page 74: Burst Timing Examples

    Change Changing TXDATAENO and TXCLKEN going low. from L to H from L to H Changing. Don't Care. Any Change State Unknown Permitted Center Does Not Line is High- Apply Impedance “Off” State WCP 53036.c-5/6/97 User Manual STEL-2176...
  • Page 75 (L) TXRDSLEN and TXSCRMEN go high on the first rising edge of TXTCLK in the User Data. (M) TXRDSLEN goes low on the rising edge of TXTCLK (last user data symbol). (N) TXSCRMEN goes low on the rising edge of TXTCLK (on the cycle of TXTCLK after the last user data bit). STEL-2176 User Manual...
  • Page 76 If bit 6 of Block 2 Register 36 is a "1" then the rising edge of DATAENO will be delayed by eight cycles of TXBITCLK (dotted line). This is required if the Reed- Solomon encoder is used. STEL-2176 User Manual...
  • Page 77 If bit 6 of Block 2 Register 36 is a "1" then the rising edge of DATAENO will be delayed by eight cycles of TXBITCLK (dotted line). This is required if the Reed- Solomon encoder is used. STEL-2176 User Manual...
  • Page 78 PI 1 PQ 1 PI 0 PQ 0 PI 1 PQ 1 PI 0 PQ 0 UI 1 UQ 1 UI 0 UQ 0 UI 1 UQ 1 UI 0 UQ 0 GI 1 GQ 1 GI 0 GQ 0 GI 1 GQ 1 GI 0 GQ 0 GUARD TIME PREAMBLE USER DATA GUARD TIME TXDIFFEN NOTE 1 TXRDSLEN TXSCRMEN TXSYMPLS TXDATAENO NOTE 2 NOTE 2 WCP 53824.c-12/5/97 STEL-2176 User Manual...

  • Page 79: Recommended Interface Circuits

    Transmitter Description RECOMMENDED INTERFACE CIRCUITS SLAVE MODE INTERFACE TSDATA TXTSDATA CLKEN TXCLKEN TXDATAENO STEL-2176 DATAEN TXDATAEN DIFFEN TXDIFFEN FCWSEL TXFCWSEL TCLK TXTCLK WCP 52995.c-5/2/97 MASTER MODE INTERFACE TSDATA TXTSDATA BITCLK DATAENI TXDATAENI STEL-2176 DIFFEN TXDIFFEN TXTCLK TXCLKEN* WCP 52115A.c 5/2/97 TXCLKEN may be turned off between bursts to conserve power as long as it is kept on until after TXDATAENO goes low.
  • Page 80 Information in this document is provided in connection with warranty, relating to sale and/or use of Intel® products in- Intel® products. No license, express or implied, by estoppel cluding liability or warranties relating to fitness for a particu- or otherwise, to any intellectual property rights is granted by lar purpose, merchantability, or infringement of any patent, this document.

Table of Contents