Composite Clock Signals; Backplane Connections - ADC PG-PLUS PCS-718 Technical Practice

Composite Clock Signals

C C
OMPOSITE LOCK
Composite clock signals are a 64 kHz bipolar clock with 8 kHz bipolar violations, that define the bit and byte
boundaries of DDS data as it is transferred within a CO. In support of DDS interfaces, PG-Plus defines two
composite clock interfaces at the PAU/PMU card slot. The PAU/PMU selects the clock and translates it into bit
and byte clocks, which it then distributes to the COLUs. Wire-wrap pins on the backplane allow the composite
clock source to be terminated or daisy-chained to another shelf.
B C
ACKPLANE ONNECTIONS
Each shelf supports the connection of up to twelve COLUs or six FICOLUs, two PMX units, and one PAU or
PMU. The backplane of the PCS-718 List 1 contains the connectors shown in
external to the COT shelf should follow the provisions of the current edition of the National Electrical Code and
applicable local codes.
P3
J4-J15
J22 TB1
Information in Tables 2 through 17 can be used for diagnostic and troubleshooting procedures under the
direction of an authorized ADC technical support representative.
2
S
IGNALS
P2
P5
Figure 2. PCS-718 Shelf Backplane
January 6, 2003
Figure 2
J3 P1
J20 HDSL pins J2
SCP-PCS718-010-06H
and Table 1. Wiring
Alarm relay
pins
J1
Composite
clock pins
Test tip, ring &
EXT ACO pins
J21
PCS-718 List 1