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Pin
Signal
11
Vin LED
12
D0
13
Vin Imager
14
D1
15
D2
16
D3
17
D4
18
D5
19
D6
20
D7
21
Pixel Clock (PCLK)
Electrical Interface Considerations
When designing the host system circuitry with a switched V
into the imager I/O lines. Leakage back into the imager I/O causes the imager V
pull-ups, protection diodes, and parasitic FET diodes. This results in unwanted current draw and causes the imager's power up
reset system to fail. A power up reset failure causes the imager to behave erratically and it may not respond correctly to I
commands.
1 - 4
Description
+3V to +9V - Power supply input for LED illumination and aiming.
Output - Pixel data. Data lines change on each falling edge of pixel clock. Data is considered valid on
the rising edge of pixel clock.
Vin Imager, +3.3V - Power supply for the imager. Care must be taken to ensure this supply is heavily
decoupled and is protected from cross coupling to high frequency signals of the processing/decoding cir-
cuitry. A broad band filter may be needed to obtain adequate isolation. See
for the Power Supply
on page C-1.
When designing the host system circuitry with a switched V
leakage path from the host into the imager I/O lines. Leakage back into the imager I/O causes the
imager V
to be back powered via the imager's internal pull-ups, protection diodes, and parasitic FET
In
diodes. This results in unwanted current draw and the imager's power up reset system will fail. The
imager behaves erratically and may not respond correctly to I2C commands when there is a power up
reset failure.
Output - Pixel data. Data lines change on each falling edge of pixel clock. Data is considered valid on
the rising edge of pixel clock.
Output - Imager timing signal that clocks pixel data. Data is valid on the rising edge of this signal.
imager, you must make sure there is no leakage path from the host
In
imager, you must guarantee there is no
In
to be back powered via the imager's internal
In
IMAGETEAM™ 4X00 Series Integration Manual
Considerations and Methods
2
C
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