ECS K7VTA2 User Manual page 36

DRAM Clock (100 MHz)
This item enables you to manually set the DRAM Clock. We recommend that
you leave this item at the default value.
DRAM Timing (Manual)
Set this to the default value to enable the system to automatically set the
SDRAM timing by SPD (Serial Presence Detect). SPD is an EEPROM chip on
the DIMM module that stores information about the memory chips it contains,
including size, speed, voltage, row and column addresses, and manufacturer.
If you disable this item, you can use the following three items to manually set
the timing parameters for the system memory
SDRAM Cycle Length (3)
When synchronous DRAM is installed, the number of clock cycles of CAS
latency depends on the DRAM timing. We recommend that you leave this item
at the default value.
Bank Interleave (4 Bank)
Enable this item to increase memory speed. When enabled, separate memory
banks are set for odd and even addresses and the next byte of memory can
be accessed while the current byte is being refreshed.
DRAM Command Rate (2T Command)
This item enables you to specify the waiting time for the CPU to issue the next
command after issuing the command to the DDR memory. We recommend
that you leave this item at the default value.
Press <Esc> to return to the Advanced Chipset Features page.
AGP & P2P Bridge Control
Scroll to this item and press <Enter> to view the following screen:
CMOS Setup Utility – Copyright (C) 1984 – 2001 Award Software
AGP Aperture Size
AGP Mode
AGP Driving Control
x AGP Driving Value
AGP Fast Write
AGP Master 1 WS Write
AGP Master WS Read
↑ ↓ → ← : MoveEnter : Select
F5:Previous Values
AGP Aperture Size (64 MB)
This item defines the size of the aperture if you use an AGP graphics adapter.
The AGP aperture refers to a section of the PCI memory address range used
AGP & P2P Bridge Control
[64M]
[4X]
[Auto]
DA
[Disabled]
[Disabled]
[Disabled]
+/-/PU/PD:Value: F10: Save ESC: Exit
F6:Fail-Safe Defaults
32
Item Help
Menu Level
F1:General Help
F7:Optimized Defaults