Counters Section - IBM 360 Manual

Figure 24. Possible Decoder Input and Output Values
Decoder Input
1 Wait
2 Mpx
4 Channel 1
8 Channel 2
Strobe — True
Wait
05)
01)
F
B
3
7
(13) (12)
D 9
5
1
Chan 1
Not Chan 1 Chan 1
Decoder Out
Figure 25. Karnaugh Map Showing Use of 4 x 16 Decoder
16
IBM Internal Use Only
Decoder Out Hub 1 1 1"
Wired to Ctr " 1" Hub
CPU
(14) (10)
E
A
6
2
8
C
0
4
Not Chan 1
Additional Self-Generated True Signals
Twenty hubs, designated ACVT BUS, on the test patch
panel may be used as a source of self-generated true signals
when the supply of +1 (A, B, C, D) and +1 (E, F, G, H)
hubs has been exhausted (Figure 26). The use of ACVT
BUS hubs as maintenance functions is described in
"Appendix F."

Counters Section

Two counter sections are on the patch panel (Figure 26).
One counter section is to the far right of operational
control panel 1 and is associated with counters 0-7. The
other counter section is to the far right of operational
control panel 2 and is associated with counters 8-15. For
each counter, two hubs are available for input connection:
the CNT hub for counting; the TMG hub for timing.
A counter is activated to count or time when an active
signal is wired to the respective CNT or TMG hub.
Counting Rate: A maximum of 1 MHz on all counters.
Increments once for each occurrence of an event up to a
maximum of one million events per second.
Timing Rate: Records the duration of an event(s) at a rate
of 1 MHz with a 1-microsecond resolution. With counters
counting at a 1-MHz timing rate, the counter overflows in
27.8 hours.
Counter Accuracy: A slight arithmetic error may occur in
the low-order positions of the Decimal Digit Display while
measuring a system function. This slight arithmetic error is
caused by signal delays through the logic blocks. For
example, total elapsed time should equal total compute
plus total wait. However, if both total compute and total
wait are monitored, the sum of the two will not, in many
instances, equal total elapsed time (to eleven digits preci­
sion) although both values are derived from the same signal
source, the wait latch. The necessity of routing total wait
through a NOT function (not total wait=total compute)
causes a slight delay. The delay may cause a discrepancy
and in some measurements may not occur at all. (This slight
discrepancy is mathematically referred to as lack of
closure.) The nominal delay time for each logic function is
given in Appendixes D and E. Each nominal delay time is
listed in nanoseconds (ns) beside each OUT hub under the
heading "Hub Title."