Detailed I/O Memory Maps - Motorola MVME167-32 User Manual

Operating Instructions
3

Detailed I/O Memory Maps

Tables 3-3 through 3-13 give the detailed memory maps for:
3-3 VMEchip2
3-4 PCCchip2
3-5 Printer
3-6 MEMC040 memory controller chip
3-7 MCECC memory controller chip
3-8 CD2401 serial chip
Note: Manufacturers' errata sheets for the various chips are available by contacting
your local Motorola sales representative. A non-disclosure agreement may be required.
3-6
3. Byte reads should be used to read the interrupt vector. These locations do not
respond when an interrupt is not pending. If the local bus timer is enabled, the
access times out and is terminated by a TEA signal.
4. Writes to the LCSR in the VMEchip2 must be 32 bits. LCSR writes of 8 or 16
bits terminate with a TEA signal. Writes to the GCSR may be 8, 16 or 32 bits.
Reads to the LCSR and GCSR may be 8, 16 or 32 bits.
5. This area does not return an acknowledge signal. If the local bus timer is enabled,
the access times out and is terminated by a TEA signal.
6. This area does return an acknowledge signal.
7. Size is approximate.
8. Port commands to the 82596CA must be written as two 16-bit writes: upper word
first and lower word second.
9. The CD2401 appears repeatedly from $FFF45200 to $FFF45FFF on the
MVME167. If the local bus timer is enabled, the access times out and is
terminated by a TEA signal.
3-9 82596CA Ethernet chip
3-10 53C710 SCSI chip
3-11 MK48T08 BBRAM/TOD clock
3-12 BBRAM configuration area
3-13 TOD clock
MVME167 Single Board Computer User's Manual