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X10SRL-F User's Manual
Chipset Configuration
North Bridge
This feature allows the user to configure the settings for the Intel North Bridge.
IIO Configuration
EV DFX (Device Function On-Hide) Feature
When this feature is set to Enable, the EV_DFX Lock Bits that are located on a
processor will always remain clear during electric tuning. The options are Dis-
able and Enable.
IIO1 Configuration
CPU SLOT3 PCI-E 3.0 X8
This item configures the PCI-E port Bifuraction setting for a PCI-E port specified
by the user. The options are Gen 1 (2.5GT/s), Gen 2 (5 GT/s), and Gen 3 (8GT/s).
CPU SLOT4 PCI-E 3.0 X8 (IN X16)
This item configures the PCI-E port Bifuraction setting for a PCI-E port specified
by the user. The options are Gen 1 (2.5GT/s), Gen 2 (5 GT/s), and Gen 3 (8GT/s).
CPU SLOT5 PCI-E 3.0 X8
This item configures the PCI-E port Bifuraction setting for a PCI-E port specified
by the user. The options are Gen 1 (2.5GT/s), Gen 2 (5 GT/s), and Gen 3 (8GT/s).
CPU SLOT6 PCI-E 3.0 X8 (IN X16)
This item configures the PCI-E port Bifuraction setting for a PCI-E port specified
by the user. The options are Gen 1 (2.5GT/s), Gen 2 (5 GT/s), and Gen 3 (8GT/s).
CPU SLOT7 PCI-E 3.0 X8
This item configures the PCI-E port Bifuraction setting for a PCI-E port specified
by the user. The options are Gen 1 (2.5GT/s), Gen 2 (5 GT/s), and Gen 3 (8GT/s).
IOAT Configuration
Enable I/OAT
Select Enable to enable Intel I/OAT (I/O Acceleration Technology), which signifi-
cantly reduces CPU overhead by leveraging CPU architectural improvements
and freeing the system resource for other tasks. The options are Enable and
Disable.
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