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2.7.4 OVP : If +5V g oes u p too mu ch , th e in du c ed v oltag e on p in 4 of T802 b ecomes larg e al so. Su ppose th at it is
ov er 18 v olts, ZD801 con du cts, pin 3 of I801 is pu lled u p ov e r 1 v olt. Th e pu lse train at pin 6 g oes down to
zero, sh u ttin g Q803 off imme diate ly .
2.7.5 SCP : If ou tpu t termin al is sh ort to g rou n d, ph oto transistor does n ot con du ct, h en ce Q806 does n ot con du ct
eith er. Th en oscilla tion of I801 is stop, sh u ttin g Q803 off immediat ely .
Line Filter
3. On-screen circuit (Circuit diagrams Main PWB)
I300 Emb eded f u n cti on .
On -screen men u screen is establish ed an d th e resu ltan t data are ou tpu t from I300 (Circu it diag ram MAIN PWB).
4. Video input circuit (Circuit diagram MAIN PWB)
Th e AC-cou pled v ideo sig n al is u se d to clamp th e black lev el at 0V).
5. Definition converter LSI peripheral circuit (Circuit diagram MAIN PWB)
I301 MRT V2 g mZAN1 is th e defi n ition A/D con v e rter LSI.
Th e a n alog R, G, B sig n a l in pu t e n tered from th e v i deo in pu t circu it i s con v ert ed in to t h e dig ital data of v ideo
sig n al th rou g h th e in corporated A/D con v erter. Bas ed on t h is con v ersion , th is de v ice performs i n terpola tion
du rin g pixel exten sion . Th e so u rce v oltag e for th is de v ice is 3.3V an d th e sy stem clock f requ en cy is 12MHz.
Th e with stan d v oltag e lev el for th e in pu t sig n al v oltag e is 3.3V an d 5V.
6. System reset, LED control circuit (Circuit diagram MAIN PWB)
6.1 Sy stem reset
Sy stem reset is perfo rmed by detec tin g th e risin g an d fallin g of th e 5V so u rce v oltag e a t I302.
6.2 LED con trol circ u it
Gre en / amb er i s li t wi th t h e c on trol s ig n a l of th e LED GREEN an d LED AM BER sig n al p in 43, 42 from I303
(Ci rcu i t di ag ram MAIN PW B).
7. E
2
PROM for PnP (Circuit diagram MAIN PWB)
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H15AAU / H15AAR Power Board Block Diagram
Rec.
Power
&
Transformer
Filter
PWM
Driver
FB
Output Rec. & Filter
Ci rcu i t D escri p ti on
A L 502
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