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PCM Timing Diagrams
Clk
Sync
Data
PCMCLK
PCMSYN
PCMIN
PCMOUT
LZT 123 7589 R1A
5. SYSTEM CONNECTOR INTERFACE
The PCM timing is shown in Figure 5.8 below and it is seen that the CPU
has 45 µs to serve an interrupt and setup data channels. Data is sent on the
falling edge of the sync pulse. The data bits in PCMULD and PCMDLD
are aligned so that the MSB in each word occurs on the same clock edge as
shown in Figure 5.9.
Figure 5.8 16-bit word within 24-bit frame
PCM signal timing is shown in Figure 5.9. The signals characteristics are
described in the tables following Figure 5.9.
t
PSS
t
PSH
Figure 5.9 PCM Timing Diagram
Name
Description
t
PCMSYN (setup) to PCMCLK (fall)
PSS
t
PCMSYN pulse length
PSH
t
PCMI (setup) to PCMCLK (fall)
DSL
t
PCMI (hold) from PCMCLK (fall)
DSH
t
PCMO valid from PCMCLK (rise)
PDLP
Name
Description
F
PCM clock frequency
PCMCLK
T
PCM clock period with 50/50 mark space ratio
PCMCLK
F
PCM sync frequency
PCMSYN
125 µs
t
DSL
MSB
X
MSB
D14
45 µs
t
DSH
D14
D13
t
PDLP
D13
Typ.
2.5
5
2.5
2.5
2.5
Typ.
200
5
8
Unit
µs
µs
µs
µs
µs
Unit
kHz
µs
kHz
35
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