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3. TECHNICAL BRIEF
AIT_BYPASS
BYPASS MODE
HIGH
(MAIN, SUB LCD)
LOW
CAMERA MODE
AIT_BYPASS
_MAIN_LCD_CS
C409
_SUB_LCD_CS
2V8_AIT_BT
C416
LGE Internal Use Only
1V8_AIT_CORE
H5
H6
C402
0.01u
D3
E10
J3
DATA00
H3
DATA01
K4
DATA02
J4
DATA03
K5
DATA04
J5
DATA05
K6
DATA06
J6
DATA07
K10
DATA08
J9
DATA09
H10
DATA10
H9
DATA11
G10
DATA12
G9
DATA13
G8
DATA14
F10
DATA15
K7
K1
J1
nRD
K2
nWR
J7
NA
ADD01
J8
K3
nAIT_RESET
K8
R404
J10
100K
F2
C_RST
K9
C415
1000p
J2
AIT_13M
G3
H4
1u
Figure 3.6.3 AIT701G CIRCUIT
CAMERA CTL IC
U402
E9
PGPIO0
D9
PGPIO1
C10
PGPIO2
B9
VDD_CORE
PGPIO3
A7
PGPIO4
B7
GND_CORE
PGPIO5
F9
PGPIO6
D10
PGPIO7
A10
PSCAN_EN
PLCD0
B10
PTEST_EN
PLCD1
A9
PLCD2
C9
PLCD3
D8
PLCD4
A8
PLCD5
B8
PHD0
PLCD6
C8
PHD1
PLCD7
C7
PHD2
PLCD8
C6
PHD3
PLCD9
B6
PHD4
PLCD10
C5
PHD5
PLCD11
B5
PHD6
PLCD12
A6
PHD7
PLCD13
C4
PHD8
PLCD14
A5
PHD9
PLCD15
B4
PHD10
PLCD16
C3
PHD11
PLCD17
PHD12
AIT701G
F8
PHD13
GND_IO2
E8
PHD14
VDD_IO2
A2
PHD15
PLCD2_CS_
B2
PLCD1_CS_
A3
PLCD_RD_
B3
PLCD_A0
A4
PHLCD_BY
PLCD_WE_
E3
PHCS_
PHSYNC
G1
PHRD_
PVSYNC
E2
PHWE_
PD0
E1
PHLCD_A0
PD1
D1
PHINT
PD2
D2
PD3
C2
PRST_
PD4
C1
PD5
A1
PHLCD2_CS_
PD6
B1
PD7
PHGPIO_CS_
H1
PSEN
H2
PSDA
G2
PS_RST_
PSCK
F3
PHWAIT_
PDCLK
F1
PMCLK
PPXL_CLK
H8
VDD_IO0
VDD_IO1
H7
GND_IO0
GND_IO1
EUSY0318501
Copyright © 2008 LG Electronics. Inc. All right reserved.
- 30 -
R401
LCD_VSYNC_OUT
0
L_DATA00
L_DATA01
L_DATA02
L_DATA03
L_DATA04
L_DATA05
L_DATA06
L_DATA07
L_DATA08
L_DATA09
L_DATA10
L_DATA11
L_DATA12
L_DATA13
2V8_AIT_BT
L_DATA14
L_DATA15
L_SUB_LCD_CS
L_MAIN_LCD_CS
C407
1u
LCD_RS
LCD_WR
C_HS
C_VS
C_CD00
C_CD01
C_CD02
C_CD03
C_CD04
C_CD05
C_CD06
C_CD07
CAM_PWR_EN
2V8_AIT_BT
C_SDA
C_SCK
C_MCLK
C_PCLK
C417
C418
C419
NA
NA
1u
Only for training and service purposes
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