Ic Pin Function Description - Sony BDP-BX37 Service Manual

IC PIN FUNCTION DESCRIPTION

MAIN SYSTEM CONTROL PIN FUNCTION (MB-134 BOARD IC101: CXD9983GG/CXD9984GG)
Pin Symbol Type
A1 FESFDO I/O
A3 VOUTD1 I/O
A5 VOUTD5 I/O
A7 VOUTD9 I/O
A9 VOUTD12 I/O
A11 VIND0 I/O
A13 VIND12 I/O
A15 VIND16 I/O
A17 GPIO1 I/O
A19 SPDIF I/O
A21 SPBCK I/O
A23 AVDD12_27 MPLL Power
A25 NS_XTALI O
A27 CH1_M Analog
A29 CLK_M Analog
A31 DACOUT4 Analog
A33 DACOUT1 Analog
A35 VCLK I/O
A37 UARXD I/O
A39 ETRXD3 I/O
A41 ETRXD0 I/O
A43 ETRXCLK I/O
B2 FESFCS I/O
B4 VOUTD3 I/O
B6 VOUTD7 I/O
B8 VOUTD10 I/O
B10 VOUTD14 I/O
B12 VIND4 I/O
B14 VIND14 I/O
B16 VINHSYNC I/O
B18 GPIO3 I/O
B20 SPLRCK I/O
B22 AOBCK I/O
B24 AVDD12_DMPLL Power
B26 CH2_M Analog
B28 CH0_M Analog
B30 EXT_CAP Analog
B32 DACOUT3 Analog
B34 VDATA I/O
B 3 6 R I / I O
B38 ETMDIO I/O
B40 ETRXD1 I/O
B42 ETRXER I/O
C1 FE_SFCLK
I/O
C3 FESFDI I
C5 VOUTD4 I/O
C7 VOUTD8 I/O
C9 VOUTD11 I/O
C11 VOUTD15 I/O
C13 VIND11 I/O
C15 VIND15 I/O
C17 GPIO0 I/O
C19 GPIO2 I/O
C21 SPMCLK I/O
C23 AOSDATA0 I/O
C 2 5 N S _ X T A L O I
C27 CH1_P Analog
C29 CLK_P Analog
C31 DACOUT5 Analog
C33 DACOUT2 Analog
C35 MRESET_ O
C37 ETCOL I/O
C39 ETRXD2 I/O
C41 ETTXCLK I/O
C43 ETTXD0 I/O
3.3V LVTTL I/O,
D2 FE_GIO11
D4
FESFCK I/O
D6 VOUTD6 I/O
D8 VOUTD0 I/O
D10 VOUTD13 I/O
D12 VIND1 I/O
D14 VIND13 I/O
D16 VINCLK I/O
D18 VIND17 I/O
D20 AOSDATA5 I/O
SECTION 6
Description
Serial Data Input to Front_End Serial Flash
NC
NC
NC
NC
NC
NC
NC
GPIO
START-BIT
SPDIF Digital Audio Out
SPDIF in Bit Clock
1.2V Analog Power for PLL
27MHz Crystal Out
HDMI TX data 1 differential pair (M)
HDMI TX clock differential pair (M)
DAC Output
DAC Output
VFD Clock (IF_SCK)
RS232 RX
CPU_UARXD
Receive Data from the PHY
Receive Data from the PHY
Receive Clock from the PHY
Front-END Serial Flash Chip Select
NC
NC
NC
NC
GPIO
DAC_XRST
NC
NC
GPIO
USB_VBUS_PCONT2
SPDIF in Left-Right Clock
Audio Out Bit Clock
1.2V Analog Power for DMPLL
HDMI TX data 2 differential pair (M)
HDMI TX data 0 differential pair (M)
NC
DAC Output
VFD Data (IF_SDO)
Infrared Input
Management Data INPUT/OUTPUT from/to the MDIO pin
Receive Data from the PHY
Receive Error Signal from the PHY
Serial Flash's Clock OUTPUT
NC
Serial Data Output to Front-END Serial Flash
NC
NC
NC
NC
NC
NC
GPIO
SYSCON_REQ
GPIO
XIF_CS
SPDIF in Master Clock
Audio Out Serial Data 0
2 7 M H z C y r t s l a n I
HDMI TX data 1 differential pair (P)
HDMI TX clock differential pair (P)
DAC Output
DAC Output
Front-End Power ON Reset
Collision Detect From the PHY
Receive Data from the PHY
Transmit Clock from the PHY
Transmit Data from the PHY
UTXD.
FE RS232 Serial Transmit data.
NC
Front-END Serial Flash Clock
NC
NC
NC
NC
NC
NC
NC
Audio Out Serial Data 5
6-1
BDP-BX37/S270/S370/S373/S470